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From: mlajevar on 18 Jan 2010 17:33
Hello

I have the vhdl code for both amplifier-ADC and DAC of spartan3E,now I want
to combine them together.Actually the purpose is to get an analog avlue
from oscilloscope send it to FPGA(through my vhdl code for ADC ,it is
converted to digital,and via the code for DAC, it will be converted to
analog voltage)and check the analog output to see if it is similar ti the
analog input we applied to ADC at first.

I am going to consider two different states for DAC and ADC, and just to
turn around these two states.I know that SPI bus will be shared between
them ,so I konw I have to disable DAC ,while working with ADC and vice
versa.

my question is how much I have to wait(in MHz) to go from ADC state to DAC
and vice versa.

I appreciate alot if you let me know about your ideas.

thanks in advance

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From: radarman on 19 Jan 2010 10:47
On Jan 18, 4:33 pm, "mlajevar" <mahsa_lajevardi(a)n_o_s_p_a_m.yahoo.com>
wrote:
> Hello
>
> I have the vhdl code for both amplifier-ADC and DAC of spartan3E,now I want
> to combine them together.Actually the purpose is to get an analog avlue
> from oscilloscope send it to FPGA(through my vhdl code for ADC ,it is
> converted to digital,and via the code for DAC, it will be converted to
> analog voltage)and check the analog output to see if it is similar ti the
> analog input we applied to ADC  at first.
>
> I am going to consider two different states for DAC and ADC, and just to
> turn around these two states.I know that SPI bus will be shared between
> them ,so I konw I have to disable DAC ,while working with ADC and vice
> versa.
>
> my question is how much I have to wait(in MHz) to go from ADC state to DAC
> and vice versa.
>
> I appreciate alot if you let me know about your ideas.
>
> thanks in advance          
>
> ---------------------------------------        
> This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com

Are you saying you want to sample an analog input with the ADC, and
then recreate a quantized, time delayed version with the DAC? (digital
voltage follower)

That's not difficult, but you need to look at the data sheets for the
parts. Specifically, how fast can you clock data on their SPI
interfaces. This is usually specified as Tcyc. Since you mention that
both parts share the same SPI interface, it would be wise to settle on
the slower of the two. In that case, it would be a good idea to leave
a dead SPI clock when switching the chip selects, to ensure that there
isn't any contention.

If your SPI clock is fairly slow, and you don't want to incur a full
Tcyc penalty, you need to determine how fast the output is tri-stated
once you deselect the chip selects for both parts, and make sure you
wait long enough to ensure there isn't contention. You will need to
look at the read timing diagram, and find the figure that shows SDO
(output) being deasserted as CSn is deasserted. That parameter sets
the absolute floor of how fast you can switch between devices, and
should be the greater of the two.

If you ever implement any kind of digital filtering, you will probably
burn enough clocks in latency to ignore this, but be sure to check
regardless.
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