compiler output to fpga.
in [FPGA]
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From: akshayvreddy on 18 Jan 2010 19:07 Hello, I am implementing a processor design on the virtex 2 chip. The Design was done using verilog with Xilinx 10.1 and modelsim. I have a compiler of the design. My question is:is there a way to integrate the compiler output with the FPGA using modelsim simulator without actually programming the fpga. I am using a windows system and the complier is C based. Thank you Akshay --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Brian Drummond on 19 Jan 2010 07:10 On Mon, 18 Jan 2010 18:07:01 -0600, "akshayvreddy" <akshayvreddy(a)gmail.com> wrote: >Hello, >I am implementing a processor design on the virtex 2 chip. The Design was >done using verilog with Xilinx 10.1 and modelsim. I have a compiler of the >design. > >My question is:is there a way to integrate the compiler output with the >FPGA using modelsim simulator without actually programming the fpga. I am >using a windows system and the complier is C based. > >Thank you >Akshay Yes. Where is the program memory for the processor? If external memory, you can modify a memory model to load (and save) its contents from a file. I have done this by adding extra "load", "save" and "filename" ports to a memory model I originally downloaded from a memory manufacturer (Cypress), and driving them from the testbench. Actually loading an object code file is then a simple matter of programming. If you are using BRAMs, you can instantiate them and translate your object code into their INIT_nn generics. But it is much better and easier to infer a ROM as a constant array, initialised by a function (which is called during elaboration). That function could read your object file into the ROM. Or you could write another program to translate the object format into a VHDL package containing your constant array. (I don't know Verilog but I expect it can do these things too) - Brian
From: Gabor on 19 Jan 2010 09:27 On Jan 19, 7:10 am, Brian Drummond <brian_drumm...(a)btconnect.com> wrote: > On Mon, 18 Jan 2010 18:07:01 -0600, "akshayvreddy" <akshayvre...(a)gmail.com> > wrote: > > >Hello, > >I am implementing a processor design on the virtex 2 chip. The Design was > >done using verilog with Xilinx 10.1 and modelsim. I have a compiler of the > >design. > > >My question is:is there a way to integrate the compiler output with the > >FPGA using modelsim simulator without actually programming the fpga. I am > >using a windows system and the complier is C based. > > >Thank you > >Akshay > > Yes. > > Where is the program memory for the processor? > > If external memory, you can modify a memory model to load (and save) its > contents from a file. I have done this by adding extra "load", "save" and > "filename" ports to a memory model I originally downloaded from a memory > manufacturer (Cypress), and driving them from the testbench. > > Actually loading an object code file is then a simple matter of programming. > > If you are using BRAMs, you can instantiate them and translate your object code > into their INIT_nn generics. > > But it is much better and easier to infer a ROM as a constant array, initialised > by a function (which is called during elaboration). That function could read > your object file into the ROM. Or you could write another program to translate > the object format into a VHDL package containing your constant array. > > (I don't know Verilog but I expect it can do these things too) > > - Brian For Verilog, you can generate ASCII hex files for initialization using $readmemh. If you place the $readmemh in an initial block in the module where the memory is inferred, it will also work for synthesis, at least in XST 10.1
From: Jonathan Bromley on 19 Jan 2010 09:57 On Tue, 19 Jan 2010 06:27:03 -0800 (PST), Gabor wrote: >For Verilog, you can generate ASCII hex files for initialization using >$readmemh. If you place the $readmemh in an initial block in the >module where the memory is inferred, it will also work for synthesis, >at least in XST 10.1 If you're a VHDL user, you can get a simulation-only VHDL implementation of $readmem (reads exactly the same input text files) here: http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip One day, when there's less work to do, I intend to add a few more file formats to its capabilities - but for now it only knows how to mimic Verilog $readmemb/h. -- Jonathan Bromley
From: whygee on 19 Jan 2010 16:02
Jonathan Bromley wrote: > http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip > One day, when there's less work to do, I intend to add a > few more file formats to its capabilities - but for now it > only knows how to mimic Verilog $readmemb/h. It seems to be enough for simple stuff so I could use it. It is licenced under Apache2.0, is it compatible with other Free Software licences ? (and which ?) yg -- http://ygdes.com / http://yasep.org |