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From: Nico Coesel on 29 Apr 2010 15:22
austin <austin(a)xilinx.com> wrote:

>Nico,
>
>How many will you buy? How many will everyone buy?
>
>Putting anything in an FPGA device has to be backed by 1+ billion ($)
>in 2+ years for the family ... or I can't even afford to get a water
>glass at the table in the marketing restaurant.
>
>Mask sets at 22nm, and development costs, are completely out of this
>world. We may be making a FPGA device that can be programmed to do
>what you want, but we still have to serve the broadest market
>possible, so we can afford to do it at all, and still make a profit
>(reasonable ROI).
>
>Imagine putting something in the FPGA device, and getting it
>wrong...it could damage the company so severely that we could lose out
>on one, or more technology cycles to our competition.

Are you sure about that? While Microsoft and Sony where fighting to
get on the edge of technology regarding game consoles Nintendo came up
with the Wii. Inferior when it comes to performance but superior when
it comes to its controls and ease of use.

Now imagine a 32 and/or 64 pin QFN device with an ARM core, a 50k
Spartan 3 like FPGA fabric some ram and some flash. Price around $3 in
large quantities and available from every street corner (Digikey,
Farnell, RS-components, etc). Such a device would open a whole new
world. One could make a microcontroller with high speed / custom
pheripherals. This would probably take extra knowledge from a
microcontroller manufacturer. Or create a 2-die device and hook the
FPGA fabric to an external memory bus. AFAIK the Spartan 3AN series
uses 2 dies in one package.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: Michael S on 29 Apr 2010 19:39
On Apr 28, 7:16 pm, n...(a)puntnl.niks (Nico Coesel) wrote:
> austin <aus...(a)xilinx.com> wrote:
> >Stephen,
>
> >Yes.
>
> >(Sorry, I am not in Marketing, but I think you are more likely to
> >believe me regardless...)
>
> Austin,
> Pleeeeeaase have lunch with marketing tomorrow and convince them to
> get a cortex-M3 or cortex-M0 in a Spartan!
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> nico(a)nctdevpuntnl (punt=.)
> --------------------------------------------------------------

Cortex-M3 by itself without good chunk of flash memory on the same die
is not that interesting. Unfortunately, flash is not compatible with
silicon process used for modern Spartan devices.
Also, according to my understanding, Cortex-M3 Physical IP libraries
are not availably for geometries finer than 90nm.

IMHO, negotiating reasonable deal with ARM w.r.t. Cortex-M1 licensing
on Xilinx devices would make a lot more sense than incorporating
Cortex-M3. I am thinking about selling Cortex-M1X-enabled chips at
small price premium relatively to otherwise identical Spartan regular
devices. Thus low-to-mid volume customers would be isolated from ATM
licensing. High-volume customers could still buy license directly from
ARM and run it on regular Spartan. And, of course, all new Virtex
devices should be Cortex-M1X-enabled - they cost enough already to
justify that little gift to the customers.
Now how to implement it technically I don't know exactly. Probably by
mean of secret authentication key embedded both into M1X-enabled
silicon and into encrypted variant of processor IP.

P.S.
Last time I talked to Altera representatives they hinted that Altera
is going to announce exactly what you're asking for. Still, I don't
think it is a good idea. The only thing that could make it useful
would be some sort of flexible bootloader for ARM core from external
serial flash that have to act independently from the main FPGA fabric.

P.P.S.
Not that I like Xilinx decision to embed dual-Cortex-A9. Cortex-A9 is
a damn nice core, but it is too big, too hot to unpredictable (heavily
relying on two levels of cache memory and dynamic branch prediction)
and overall an overkill for sorts of applications that I want to run
within FPGA. Cortex-R4F looks like better fit. But then again, may be
Cortex-R4F is too similar feature-wise to PPC cores that they had in
previous generations of Virtex, According to my understanding, those
PPC cores were nor considered a major success story.


From: -jg on 29 Apr 2010 22:35
On Apr 30, 7:22 am, n...(a)puntnl.niks (Nico Coesel) wrote:
> Now imagine a 32 and/or 64 pin QFN device with an ARM core, a 50k
> Spartan 3 like FPGA fabric some ram and some flash. Price around $3 in
> large quantities and available from every street corner (Digikey,
> Farnell, RS-components, etc). Such a device would open a whole new
> world.

That's not really Xilinx's space, AND such a device still has to
compete with any EXISTING PLD+uC solution.

So claims of a 'whole new world' are excessive, as there are
solutions now, and have been for years.

Other players have more chance of approaching some of your wishlist,
with Cypress and Actel sampling silicon.
(& Atmel have a mask solution, if your volumes are enough)

However, the big issue remains PRICE, with neither company coming
anywhere near your price point!!

That's been the historical failing of previous players in this space
too...

-jg
From: Nico Coesel on 30 Apr 2010 03:28
-jg <jim.granville(a)gmail.com> wrote:

>On Apr 30, 7:22=A0am, n...(a)puntnl.niks (Nico Coesel) wrote:
>> Now imagine a 32 and/or 64 pin QFN device with an ARM core, a 50k
>> Spartan 3 like FPGA fabric some ram and some flash. Price around $3 in
>> large quantities and available from every street corner (Digikey,
>> Farnell, RS-components, etc). Such a device would open a whole new
>> world.
>
> That's not really Xilinx's space, AND such a device still has to
>compete with any EXISTING PLD+uC solution.
>
> So claims of a 'whole new world' are excessive, as there are
>solutions now, and have been for years.
>
> Other players have more chance of approaching some of your wishlist,
>with Cypress and Actel sampling silicon.
>(& Atmel have a mask solution, if your volumes are enough)
>
> However, the big issue remains PRICE, with neither company coming
>anywhere near your price point!!
>
> That's been the historical failing of previous players in this space
>too...

So there is a lot to be won here. I'm sure a market can be created.
Just look at how all low-cost scopes are built. Just one FPGA (usually
Altera) with their NIOS processor embedded runs the entire show.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: Kolja Sulimma on 30 Apr 2010 04:12
On 28 Apr., 20:29, austin <aus...(a)xilinx.com> wrote:
> Nico,
>
> How many will you buy?  How many will everyone buy?
>
> Putting anything in an FPGA device has to be backed by 1+  billion ($)
> in 2+ years for the family ... or I can't even afford to get a water
> glass at the table in the marketing restaurant.
>
> Mask sets at 22nm, and development costs, are completely out of this
> world.  We may be making a FPGA device that can be programmed to do
> what you want, but we still have to serve the broadest market
> possible, so we can afford to do it at all, and still make a profit
> (reasonable ROI).

This is true if you think about adding an extra device with that
feature while
still offering devices without the feature.
If the added feature is small compared to the overal size of the FPGA
the cost
analysis changes if you add it to all devices (possible starting from
a certain size).
+ there is no added mask cost
0 there is a small increase in device cost
0 a reduction in yield could be covered by selling failing devices as
not having the feature
- there is added risk of a respin because the complexity increases
- there is added engineering cost in software and hardware for the
added feature

I do not believe that you need billions in market to cover a decision
like this and that probably
is why xilinx keeps adding features to their devices.

BTW:
I really would like to see JTAG signal integrity monitoring on all
pins:
http://dspace.mit.edu/bitstream/handle/1721.1/41609/216829581.pdf
This adds virtually no real estate to the chip and every high speed
board designer will shout
"hurray" and jump into the air a couple of times.


Regards,

Kolja
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