BPSK modulation on Xilinx FPGA
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From: cs_posting on 1 Feb 2006 17:30 Ray Andraka wrote: > Alternatively, you could generate ascii binary in your external > application and past that into an array of bit_vectors directly. This is where I like verilog's include directive... no pasting required.
From: Ray Andraka on 1 Feb 2006 19:59 MikeJ wrote: > Ray, one thought - > I recently had to modify my romgen program (www.fpgaarcade.com) which > produces init strings and generics with a conversion function much as you > suggest. > However the Synplicity tool uses a different attribute style to Mentor's > Precision. I discovered that Synplicity at least will produce the correct > block ram init strings with only the generic set - no synthesis attributes > required. > > About time too .... > /Mike > Mike, Yes, it is true if you use the synplify and mentor attributes. Instead, you can set them up as user attributes using the Xilinx attribute name (INIT_XX=) so that it is tool agnostic. That indifference to which tool it is used on is also why I haven't been taking advantage of Synplicity's (pretty much still unique) ability to infer the attributes from the generics.
From: news.verizon.net on 1 Feb 2006 21:19 Ben, I used a DDS LogiCORE to generate the sine (and cosine) and then a pair of two-complementor LogiCORE to handle the BPSK; you wire the data value to the BYPASS pin. Works like a champ. Marty martin dot ryba (at) verizon dot net "Ben Marpe" <Ben.Marpe(a)gmx.de> wrote in message news:1138801274.996807.307800(a)g49g2000cwa.googlegroups.com... Hi everybody, I'm trying to implement a BPSK modulation. A sin waveform has to be generated at a given frequency (1MHz) with phase offset (binary PSK i.e. 180?) when transition occures on a data wire. Is there any "simple" LogiCORE with BPSK functionality available for my Xilinx Spartan-3 - Board ? My attempt would be a LUT in BRAM - but do I have to fill its content manualy ? The LUT content (e.g. 16bit) could drive a DAC. On the other hand, If I'm forced to use a external DAC, I might use a DDS (e.g. AD9834) with all BPSK functionality on chip... ?!? I'm interested in your ideas and suggestions ! Bye, BEN
From: Allan Herriman on 1 Feb 2006 23:35 On 1 Feb 2006 14:30:14 -0800, cs_posting(a)hotmail.com wrote: >Ray Andraka wrote: > >> Alternatively, you could generate ascii binary in your external >> application and past that into an array of bit_vectors directly. > >This is where I like verilog's include directive... no pasting >required. .... until you need two instances of the same module with different INIT values. You can't (for example) have a parameter select different INIT values. `include happens at compile time. Deferring this until elaboration time would be much more useful (for some applications). YMMV. Regards, Allan
From: Ray Andraka on 2 Feb 2006 00:24
Allan Herriman wrote: > > ... until you need two instances of the same module with different > INIT values. You can't (for example) have a parameter select > different INIT values. > > `include happens at compile time. Deferring this until elaboration > time would be much more useful (for some applications). > YMMV. > > Regards, > Allan That's an advantage of VHDL. I regularly put the parameters into a generic as an integer array so that I can have multiple instances of the same component with different init data. Doing that in verilog requires a pre-processor to parse out those and rewrite it into inline instances with different names. Kind of awkward if you ask me. If you don't want to paste, you can always write your other application so that it writes out a complete file containing a VHDL package that has the constants declared in it. Then you just need to include that package in a library statement at the top of your VHDL code. This is handy if you have something that is going to get updated often enough that pasting in presents too great an opportunity of screwing it up. Also good for throwing code over a wall. |