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From: Brian Davis on 28 Aug 2005 21:32
Andrew,
>
> Does anyone know what sort of performance can be expected
> from a CPLD in this regard?
>
Asides from the supply/clocking suggestions already made,
I'd also add the following caution: the output stages of most
programmable digital parts are not intended for producing
clean reference signals to a PLL used for low-noise RF signal
generation.

A few times over the years that I've considered doing this,
the first thing I've done is build something like a pulse output
divide-by-ten in the intended technology, driven the part with an
oscillator having known phase noise, and looked at the divider output
on both a spectrum analyzer & phase noise measurement system.

Most of the programmable parts I've measured have had output spurs
50-60 db down that vary strongly in frequency with supply voltage,
and can cross over the intended output frequency, making it impossible
to keep them out of the loop BW. ( also, the crud in the output
spectrum will generally behave differently with an even duty cycle
output than for a pulse output divider )

other (hastily conceived) random thoughts:
- what's the noise floor of your spectrum analyzer at 1 KHz?
- try using a surplus ocxo for your 10 MHz source
- if you disable the uC/SRAM, and implement a fixed divide entirely
internal to the CPLD, does the noise get any better?

have fun,
Brian

From: Andrew Holme on 29 Aug 2005 05:44
Thanks to all for the suggestions.

The ground pins were connected by threading wires through the holes, and
soldering them to the ground plane before fitting the PLCC socket.

Personally, I now think the monolithic regulator supplying U4 is the main
noise source. Thanks, Daniel. I've been pouring over Rohde and Egan,
trying to get my head round spectral density stuff. I'd appreciate it if
someone could check my math. I've calculated the equivalent noise voltage
that would have to be injected at the loop filter input (U4 output) to
produce -95 dBc/Hz at a 1 KHz offset on the VCO. The following script was
executed in SCILAB:

// Closed-loop gain from PFD output to VCO output
pd_2_vco = h/kpd/kn;

// -95 dBc/Hz
theta_rms = sqrt(10^(-95/10) * 2);

// Equivalent noise injection at PFD output (1 KHz offset)
v_rms = theta_rms / horner(pd_2_vco, 2*%pi*1000)

This gives 20nV/sqrt(Hz). Since U4 output is a 50% duty cycle square
wave(XOR PFD), presumably I would still only need 40nV/sqrt(Hz) on the
regulator output? Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05 with 100n
+ 10n hanging off its output?

Script notes:
h = Closed loop gain
kpd = PFD gain
kn = Divider gain
horner() returns magnitude of transfer function at specified freq



From: Andrew Holme on 29 Aug 2005 06:15
Andrew Holme wrote:
> regulator output? Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05
> with 100n + 10n hanging off its output?

The 78L05 datasheet quotes an output noise voltage of 40uV for 10Hz <= f <=
100 KHz with a minimum recommended load capacitance of 10n. I presume this
means 40uV peak-to-peak? I'm not sure how to convert this to RMS
nV/sqrt(Hz), but 40e-6/sqrt(100e3) = 1.26e-7 which is only 3 times my
figure.


From: Andrew Holme on 29 Aug 2005 06:34
Andrew Holme wrote:
> // Closed-loop gain from PFD output to VCO output
> pd_2_vco = h/kpd/kn;

Sorry, I think that was wrong. That h was the closed-loop gain from ref
input to vco output.

A safer way to calculate it, using the SCILAB /. operator is:

t_pd_vco = (f * kvco/s) /. (kpd * kn);

where f = loop filter transfer function.

Now I get v_rms = 793 nV/sqrt(Hz)

Hmm....


From: Winfield Hill on 29 Aug 2005 07:07
Andrew Holme wrote...
> Andrew Holme wrote:
>> regulator output? Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05
>> with 100n + 10n hanging off its output?
>
> The 78L05 datasheet quotes an output noise voltage of 40uV for
> 10Hz <= f <= 100 KHz with a minimum recommended load capacitance
> of 10n. I presume this means 40uV peak-to-peak?

Hah, it's likely rms, because that leads to a much smaller number.
Also, the NEC and Linfinity datasheets explicitly say rms.

The NSC datasheet note says, "minimum load capacitance of 0.01ýF
to limit high frequency noise," which means the output noise is
not white, which means you can't perform the usual simple sqrt-BW
calculations to obtain the noise density.


--
Thanks,
- Win
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