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From: Ken Smith on 29 Aug 2005 10:40
In article <deuq9102apv(a)drn.newsguy.com>,
Winfield Hill <Winfield_member(a)newsguy.com> wrote:
[...]
> The NSC datasheet note says, "minimum load capacitance of 0.01ýF
> to limit high frequency noise," which means the output noise is
> not white, which means you can't perform the usual simple sqrt-BW
> calculations to obtain the noise density.

Most closed loop things have a noise that rises to a peak at the gain
cross over point. This would apply to the LM7805 like devices.

In the OP's case this band of noise is almost certain to alias to exactly
where it causes the most trouble. At some output frequency, the peak near
the crossover will alias near zero. When I had a situation very like the
OPs, I argued like this:

The noise is confined to a band with a 3dB width of about 1/4 the gain
cross over and thus we can find the nV/sqrt(Hz) for the noise. (This was
true for the noise spectrum I was dealing with.)

At the frequency where the noise makes the most trouble, the noise
spectrum is shifted near zero by aliasing. In this situation, the noise
spectrum now appears flat.

The gain of the aliasing process can be measured by injecting a signal
near the frequency that is being aliased.

The frequency noise in the PLL output is mostly above the gain cross over
point of the PLL. The hardware after the PLL adds other band width
limiting effects and also may further alias this to make the final
results.

--
--
kensmith(a)rahul.net forging knowledge

From: Joerg on 29 Aug 2005 15:45
Hello Andrew,

>>regulator output? Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05
>>with 100n + 10n hanging off its output?
>
> The 78L05 datasheet quotes an output noise voltage of 40uV for 10Hz <= f <=
> 100 KHz with a minimum recommended load capacitance of 10n. I presume this
> means 40uV peak-to-peak? I'm not sure how to convert this to RMS
> nV/sqrt(Hz), but 40e-6/sqrt(100e3) = 1.26e-7 which is only 3 times my
> figure.

You could always build your own regulator or, as some say, filter the
dickens out of it.

Regards, Joerg

http://www.analogconsultants.com
From: John_H on 29 Aug 2005 15:47
What are you using to measure the phase noise? I'd hate for some troubles
to be found there.

The results you consider to be "poor" are with integer-N values to low
comparison frequencies?
Have you tried integer-N values with higher comparison frequencies?

I've wanted to put together a nice Fractional-N synth for a while but
haven't gotten around to it. One thing on my list is to have the phase
compator external (high precision analog component) and have the final stage
of the divided frequencies go through isolated single-gate registers clocked
off the VCO and Oscillator so the divided clocks have no induced noise from
my programmable device. If you insist on having the PFD in the CPLD, you
will have edge noise injected by signals elsewhere on the FPGA, notable I/O
that are nearby but also general functionality. You may be able to arrange
the system so any package noise is minimized (Xilinx has had some recent
discussions about cross-coupled noise in promoting their Virtex-4 parts).
If the CPLD has different I/O banks, you might improve the situation by
removing unrelated I/O from the I/O bank that contains the PFD.

I hope you can demonstrate some nifty results.


"Andrew Holme" <andrew(a)nospam.com> wrote in message
news:desmbt$i07$1$8302bc10(a)news.demon.co.uk...
> The dividers and the phase detector of my experimental frequency
synthesizer
> are implemented in a 15ns Altera MAX7000S CPLD. I've tried different
> multiplication factors (kN) to see how the close-in phase noise varies.
At
> a 1 KHz offset, I get:
>
> -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz)
> -95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz)
>
> Calculating the equivalent phase noise at the PFD:
>
> -82-20*log10(198) = -128 dBc/Hz
> -95-20*log10(39) = -127 dBc/Hz
>
> Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect
these
> to differ by 13 dB if the noise was mainly due to a fixed amount of time
> jitter at the PFD.
>
> I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
> (inside the CPLD) to obtain the reference frequencies. I've read these
are
> good for at least -130 dBc/Hz (before dividing down) so I'm a bit
> dissappointed with my noise levels. Maybe it got a bit too hot when I
> soldered it to the ground plane! I must try another....
>
> Googling for "altera cpld jitter" doesn't turn-up much, and they don't
> mention jitter in the datasheet. Does anyone know what sort of
performance
> can be expected from a CPLD in this regard? I don't know if the CPLD, or
my
> circuit lash-up is the root cause.
>
> A full write-up of the project can be found at
> http://www.holmea.demon.co.uk/Frac2/Main.htm It has a fractional-N
> capability, but noise-levels are the same in integer-N mode with the
> external RAM disabled.
>
> Thanks,
> Andrew.


From: Andrew Holme on 29 Aug 2005 17:25
John_H wrote:
> What are you using to measure the phase noise? I'd hate for some
> troubles to be found there.

I'm using a Marconi 2382 spectrum analyzer. At current levels, I can see it
no problem wthout any special test setup. If I get another 10 or 20 dB
improvement, then I'd need a more sophisticated method.

> The results you consider to be "poor" are with integer-N values to low
> comparison frequencies?
> Have you tried integer-N values with higher comparison frequencies?

I've tried 100 KHz and 500 KHz comparison frequencies.

Yesterday, I thought the phase noise might be due to the reference or the
PFD, and when I estimated the dBc/Hz at the PFD, I thought the numbers were
poor. Now, I'm not so sure the CPLD is the biggest problem. I think I may
just need better power supply filtering after the monolithic regulators.

> I've wanted to put together a nice Fractional-N synth for a while but
> haven't gotten around to it. One thing on my list is to have the
> phase compator external (high precision analog component) and have
> the final stage of the divided frequencies go through isolated
> single-gate registers clocked off the VCO and Oscillator so the
> divided clocks have no induced noise from my programmable device. If
> you insist on having the PFD in the CPLD, you will have edge noise
> injected by signals elsewhere on the FPGA, notable I/O that are
> nearby but also general functionality. You may be able to arrange
> the system so any package noise is minimized (Xilinx has had some
> recent discussions about cross-coupled noise in promoting their
> Virtex-4 parts). If the CPLD has different I/O banks, you might
> improve the situation by removing unrelated I/O from the I/O bank
> that contains the PFD.

I see what you're saying about implementing the PFD externally, and
re-synchronising the divider outputs to the VCO and REF clocks. No doubt
that would deliver the ultimate in performance. What sot of PFD did you
have in mind?


From: John_H on 29 Aug 2005 18:35

"Andrew Holme" <andrew(a)nospam.com> wrote in message
news:devuni$a0t$1$830fa17d(a)news.demon.co.uk...
<snip>
> I'm using a Marconi 2382 spectrum analyzer. At current levels, I can see
it
> no problem wthout any special test setup. If I get another 10 or 20 dB
> improvement, then I'd need a more sophisticated method.

You're taking the bandwidth into account? Usually spectrum analyzers like
to report in dBm - bandwidhts need to be considered along with slopes to
determine "real" dBc/Hz or dBc/sqrt(Hz).

<snip>
> > Have you tried integer-N values with higher comparison frequencies?
> I've tried 100 KHz and 500 KHz comparison frequencies.

You might find a trend in noise improvement as you increase the comparison
frequency, averaging the effect of nonlinearities of the system. By doing
your initial investigation at integer-N values, the spurs that "should" be
filtered out aren't a concern in wideband noise measurements. Only when you
know what to expect at higher frequencies can you figure out what an ideal
reference frequency may be.

I consider the biggest advantage to using fractional-N synthesis
(particularly with programmable logic) is the high comparison frequencies
used to get the desired ratios. If you're using a 10 MHz oscillator, use
that value undivided and check the 20 MHz performance with a VCO
divide-by-2. Step back to 19.8 MHz with the fractional 1.98 value and see
if there's noticeable degredation from the noise shaping for close-in phase
noise.

> Yesterday, I thought the phase noise might be due to the reference or the
> PFD, and when I estimated the dBc/Hz at the PFD, I thought the numbers
were
> poor. Now, I'm not so sure the CPLD is the biggest problem. I think I
may
> just need better power supply filtering after the monolithic regulators.

You noted an improvement going from 100k to 500k comparison frequencies. If
power-supply noise were dominant, I wouldn't expect to see that 13 dB change
in phase noise.

<snip>
> What sort of PFD did you have in mind?

For my own synth design, I'd like to use a clock generator with integrated
PFD/VCO with good characterization so I know what to expect when running 50
MHz (or similarly large) reference frequencies. The MiniCircuits devices
are great to prototype with or do one-off pieces of test gear, but when
going for those kinds of designs the actual AD9901 might be the most
productive way to go.

The integrated PFD/VCO devices tend to generate much higher frequency VCOs
internally (to be entirely on the silicon) but are often divided down
internally to give a "usable" output frequency.

I think the part I was looking at most recently (because of the integrated,
programmable loop filters) was an idt device - the part number eludes me at
the moment (some of this research is at home). With an appropriate clock
generator (ideally single channel), the reference frequency from the
fractional-N generator can internally go through an integer-N multiply to
get to the desired output frequency. All the intelligence in in the
FPGA/CPLD, all the analog precision is in the clock generator.


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