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From: sp_mclaugh on 1 Nov 2006 13:22
sp_mcla...(a)yahoo.com wrote:
> Type 2 PLL ?

Apologize for the extra post, but I meant Type 2 phase detector

From: Jan Panteltje on 1 Nov 2006 13:49
On a sunny day (1 Nov 2006 10:21:12 -0800) it happened sp_mclaugh(a)yahoo.com
wrote in <1162405271.882065.85910(a)f16g2000cwb.googlegroups.com>:

>Perhaps there is some way to make a voltage-controlled relaxation
>sawtooth oscillator (where the threshold voltage for "resets" is
>somehow adjustable by a voltage) and use a Type 2 PLL ? ie, the type
>which only looks at the *edges* of the oscillator and reference input?
>Just a guess.

It is relatively simple, charge a C, control the current source, use a
voltage comparator to trigger a flip flop that then discharges the C immediately.


I actually published one here a week or so ago.

----------------------------------------- +12V
| | |
[ ] [ ] R1 [ ]
| | |
| |</ e |
|---| PNP T2 | T3
| |\ c |--
T1 | --------\ | unijucntion transistor
| | |--
|---- d | |------------ B pulse out
----| JFET |---A |
|---- s | [ ]
| === |
Uin [ ] | C1 |
| | |
------------------------------------------- 0V



Capacitor C1 will be charged by constant current source T2.
The amount of current determines how fast T3 will trigger.

Current source T2 is controlled by T1

[] are resistors (European symbol).

Uin controls the frequency.

At point 'A' there is the linear ramp output.
The pulse out at point 'B' can be used as sample pulse in a phase discriminator.

Note that the amplitude of the ramp (sawtooth) is not depending on the frequency.

I have actually used UJT timebases in monitor, TV, and video camera design, 1968 or so.

You must feed 'A' into a high impedance.




From: Peter Bennett on 1 Nov 2006 15:51
On 31 Oct 2006 23:41:26 -0800, sp_mclaugh(a)yahoo.com wrote:


>As for the vertical deflection, it should look like a "staircase",
>right? Of course, there would be a sharp downward line after each
>"staircase" for the vertical retrace. How is this waveform generated?
>My initial guess, again, would be a simple integrator whose input was
>the horizontal sync pulses. It would reset itself on each vertical sync
>pulse.

No - the vertical scan is a smooth sawtooth - the horizontal scan
lines are not truly horizontal - instead they slope downwards slightly
as they cross the screen.


--
Peter Bennett VE7CEI
email: peterbb4 (at) interchange.ubc.ca
GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html
Newsgroup new user info: http://vancouver-webpages.com/nnq
From: Jan Panteltje on 1 Nov 2006 16:01
On a sunny day (Wed, 01 Nov 2006 12:51:36 -0800) it happened Peter Bennett
<peterbb(a)nowhere.invalid> wrote in
<u32ik2lkbs5nt4dl5ph40ck4fcraf1a7ub(a)4ax.com>:

>On 31 Oct 2006 23:41:26 -0800, sp_mclaugh(a)yahoo.com wrote:
>
>
>>As for the vertical deflection, it should look like a "staircase",
>>right? Of course, there would be a sharp downward line after each
>>"staircase" for the vertical retrace. How is this waveform generated?
>>My initial guess, again, would be a simple integrator whose input was
>>the horizontal sync pulses. It would reset itself on each vertical sync
>>pulse.
>
>No - the vertical scan is a smooth sawtooth - the horizontal scan
>lines are not truly horizontal - instead they slope downwards slightly
>as they cross the screen.

Yoa yoa, I put a piece of paper under the right side of the set.
From: sp_mclaugh on 1 Nov 2006 19:13
Thanks, Jan, for the schematic you included, and the explanation from
the previous post. That is what I was looking for. I had only been
exposed to PLL's as used in FM demodulation (with an analog multiplier
and a loop filter). After some more research and your posts, I think I
understand what is going on (hopefully).

As an aside, for VGA (not broadcasted television), do we really even
need the PLL? I'm not suggesting using a non-locked local oscillator,
I'm just suggesting using the sync pulses directly to dischage the
capacitor. I wouldn't think that there would be much noise on the sync
lines. (Not that I would do this if I was a commercial VGA monitor
producer, it's just another "what if" question).

Also, thanks to you and the other poster for clearing up my error about
the vertical deflection (ie, the bit I wrote about it looking like a
"staircase"). I hadn't noticed that when I first read my VGA
literature.

Now to apply this information to what I'm doing with VGA:

So if a CRT was built using the type of circuit you described, the
*duration* of the h-sync pulses shouldn't matter, so long as they are
long enough to bring the current in the inductor back to zero, right?
(or bring it negative, or whatever corresponds to the left of the
screen). If, for example, I continued to assert h-sync during the back
porch, I would expect the image to simply by shifted so that it went
*completely* to the left edge of the screen. (Exactly as if I didn't
include a back porch at all, and shifted the video data ahead by the
corresponding amount).

Perhaps that sounds tedious - something nobody would ever do. I guess a
more practical circumstance might be if my VGA driving circuit ran at a
frequency which wasn't an integer multiple of the desired dot clock.
Depending on how slow the clock was, one might be presented with
problems trying to keep within the timing specifications. It would be
nice to know what behavior to expect from the CRT if h-sync or v-sync
pulses were too long/short or at too high/low of a frequency. Hence my
reason for digging into the "guts" of the deflection circuitry.

And for a strictly fixed-frequency monitor, if I wanted to just use the
upper-left portion of the screen, could I just generate h-sync and
v-sync pulses twice as fast? (This would, of course, mean that I'm
sending the "wrong" sync frequencies to a fixed-frequency monitor. I'm
not sure whether there any any components that could fail by doing
this.)

Thanks again.
-Sean

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