Prev: Digital automotive tach circuit?
Next: BDM download cables - compatibility issues.
From: Jan Panteltje on 2 Nov 2006 06:02
On a sunny day (1 Nov 2006 16:13:34 -0800) it happened sp_mclaugh(a)yahoo.com
wrote in <1162426414.492459.247670(a)k70g2000cwa.googlegroups.com>:

>As an aside, for VGA (not broadcasted television), do we really even
>need the PLL? I'm not suggesting using a non-locked local oscillator,

In theory at _one_ frequency, no PLL needed.
If the oscillator needs to lock over a high frequency a PLL circuit as I
did show has advantages.
But most important is, that if your sync was to interrupt, the scanning
of the CRT would stop, and the spot would burn in in the centre.
You want a picture even without input signal, my monitor then displays
a warning message about 'check signal cable'.
A CRT can burn in in a fraction of a second when all the energy goes to one
focussed spot on the screen.


>Now to apply this information to what I'm doing with VGA:
>
>So if a CRT was built using the type of circuit you described, the
>*duration* of the h-sync pulses shouldn't matter, so long as they are
>long enough to bring the current in the inductor back to zero, right?

The H sync time is specified in the spec, but it is _not_ the H sync
time that drives the H switch directly, that would be very dangerous,
some disturbance and the current in the horizontal output stage would
kill it.

The time ratio (on / off) of the H stage is set in the drive circuit.

-------- ------------ ------- H sync pulse, leading edge is used.
| | | |
- -

on
-------- ----------- ----- Horizontal drive
| | | |
-- --
off


black ---- ----
| | | |
------- --------- ----- blanking to CRT


||||||| |||||||||| |||| video luminance signal


>(or bring it negative, or whatever corresponds to the left of the
>screen). If, for example, I continued to assert h-sync during the back
>porch, I would expect the image to simply by shifted so that it went
>*completely* to the left edge of the screen. (Exactly as if I didn't
>include a back porch at all, and shifted the video data ahead by the
>corresponding amount).

Normally the ;leading edge of the H sync is used for trigger,
(phase aligned with a new scan), so the timebase circuit has some time to start.
If you make H too long in a composite signal it gets into the picture
as ultra-black.
If it is external sync you may notice very little, as normally only the
leading edge is used.



>Perhaps that sounds tedious - something nobody would ever do. I guess a
>more practical circumstance might be if my VGA driving circuit ran at a
>frequency which wasn't an integer multiple of the desired dot clock.
>Depending on how slow the clock was, one might be presented with
>problems trying to keep within the timing specifications. It would be
>nice to know what behaviour to expect from the CRT if h-sync or v-sync
>pulses were too long/short or at too high/low of a frequency. Hence my
>reason for digging into the "guts" of the deflection circuitry.

That depends on the PLL design.
These days there is (hopefully!) a frequency discriminator that checks for
a valid range (my monitor switches the HV and scanning off, if sync is out of range).
Else it would blow up.

>And for a strictly fixed-frequency monitor, if I wanted to just use the
>upper-left portion of the screen, could I just generate h-sync and
>v-sync pulses twice as fast?

Simpler even, you use the same (correct) H and V frequency, but send the
info at double speed (double pixel clock) in the first line, and
wait the other half line time, and send the info in the second line you
have at double speed, etc, until you run out of lines.
This assumes your monitor can display those double high frequencies (detail).
This also shows you need _half_ the number of lines in your original!
On a 600 line height screen you have only 300 lines for half the picture.



> (This would, of course, mean that I'm
>sending the "wrong" sync frequencies to a fixed-frequency monitor. I'm
>not sure whether there any any components that could fail by doing
>this.)

So no need to do that.
From: Ancient_Hacker on 2 Nov 2006 08:37

Jan Panteltje wrote:

> >No - the vertical scan is a smooth sawtooth - the horizontal scan
> >lines are not truly horizontal - instead they slope downwards slightly
> >as they cross the screen.
>
> Yoa yoa, I put a piece of paper under the right side of the set.

That's only on TV sets that did not pay the licensing fee for the
patent "straightening the picture by turning the yoke 1/525th of the
way to the left".

From: Fred Bartoli on 2 Nov 2006 09:21
Ancient_Hacker a ?crit :
> Jan Panteltje wrote:
>
>>> No - the vertical scan is a smooth sawtooth - the horizontal scan
>>> lines are not truly horizontal - instead they slope downwards slightly
>>> as they cross the screen.
>> Yoa yoa, I put a piece of paper under the right side of the set.
>
> That's only on TV sets that did not pay the licensing fee for the
> patent "straightening the picture by turning the yoke 1/525th of the
> way to the left".
>

This patent is useless here where the hot thing is to tilt the yoke by
1/625th.


--
Thanks,
Fred.
From: Frithiof Andreas Jensen on 3 Nov 2006 05:07

<sp_mclaugh(a)yahoo.com> wrote in message
news:1162403890.265240.205130(a)m7g2000cwm.googlegroups.com...

> Yes, I actually did realize that, but I guess I didn't word my post
> quite right. If you like, add a voltage-controlled current source to
> the output I described. Like you said down below, that might be very
> impractical (ie, power-hungry, and stressful on components). But my
> main interest is in generating the "shape" of the deflection waveform,
> even if it wouldn't be a smart way to build a real CRT.

Philips USED TO have a pdf-format book of application notes "Power Semiconductor
Applications" - but I cannot find it anymore amongst the corprat's "RAH RAH
RAH: Look How Great WE Are" Garbage on the web site! Maybe you have more luck
and/or patience.



From: joseph2k on 3 Nov 2006 23:36
Jan Panteltje wrote:

> On a sunny day (1 Nov 2006 16:13:34 -0800) it happened
> sp_mclaugh(a)yahoo.com wrote in
> <1162426414.492459.247670(a)k70g2000cwa.googlegroups.com>:
>
>>As an aside, for VGA (not broadcasted television), do we really even
>>need the PLL? I'm not suggesting using a non-locked local oscillator,
>
> In theory at _one_ frequency, no PLL needed.
In practice Yes, it is required to keep the horizontal and vertical blanking
from wandering all over the screen.

> If the oscillator needs to lock over a high frequency a PLL circuit as I
> did show has advantages.
> But most important is, that if your sync was to interrupt, the scanning
> of the CRT would stop, and the spot would burn in in the centre.

Not at all, the horizontal and vertical oscillators would free run as
designed. Moreover the anode high voltage is derived from the horizontal
sweep and no sweep translates sooner or later to no anode voltage.

> You want a picture even without input signal, my monitor then displays
> a warning message about 'check signal cable'.
> A CRT can burn in in a fraction of a second when all the energy goes to
> one focussed spot on the screen.

I have not had quick burn problems with my o'scopes. YMMV

>
>
>>Now to apply this information to what I'm doing with VGA:
>>
>>So if a CRT was built using the type of circuit you described, the
>>*duration* of the h-sync pulses shouldn't matter, so long as they are
>>long enough to bring the current in the inductor back to zero, right?

They have to synchronize the horizontal oscillator, and for color TV gate
the chroma burst PLL. The other issues are internal to the display.

>
> The H sync time is specified in the spec, but it is _not_ the H sync
> time that drives the H switch directly, that would be very dangerous,
> some disturbance and the current in the horizontal output stage would
> kill it.
>
> The time ratio (on / off) of the H stage is set in the drive circuit.
>
> -------- ------------ ------- H sync pulse, leading edge is used.
> | | | |
> - -
>
> on
> -------- ----------- ----- Horizontal drive
> | | | |
> -- --
> off
>
>
> black ---- ----
> | | | |
> ------- --------- ----- blanking to CRT
>
>
> ||||||| |||||||||| |||| video luminance signal
>
>
>>(or bring it negative, or whatever corresponds to the left of the
>>screen). If, for example, I continued to assert h-sync during the back
>>porch, I would expect the image to simply by shifted so that it went
>>*completely* to the left edge of the screen. (Exactly as if I didn't
>>include a back porch at all, and shifted the video data ahead by the
>>corresponding amount).

Please consider, that inductor (yoke) voltage is e = -L * di/dt. Thus a
very asymetrical current sawtooth is created by a voltage square wave that
is a bit asymmetrical. After the flyback pulse drives the yoke current to
the max -x position, the damper tube monotonically reduces the yoke current
to about zero. Then the horizontal output turns on and continues the sweep
from midscreen to the other edge. Then it cuts off and the resulting high
voltage spike reverses the current in the yoke very quickly.

>
> Normally the ;leading edge of the H sync is used for trigger,
> (phase aligned with a new scan), so the timebase circuit has some time to
> start. If you make H too long in a composite signal it gets into the
> picture as ultra-black.
> If it is external sync you may notice very little, as normally only the
> leading edge is used.
>
>
>
>>Perhaps that sounds tedious - something nobody would ever do. I guess a
>>more practical circumstance might be if my VGA driving circuit ran at a
>>frequency which wasn't an integer multiple of the desired dot clock.
>>Depending on how slow the clock was, one might be presented with
>>problems trying to keep within the timing specifications. It would be
>>nice to know what behaviour to expect from the CRT if h-sync or v-sync
>>pulses were too long/short or at too high/low of a frequency. Hence my
>>reason for digging into the "guts" of the deflection circuitry.

V-sync is not nearly so straight forward. Google for NTSC and look for a
thorough explanation of vertical sync; to be worthwhile it will include
"equalizing pulses". Now there is a can of worms for you.

>
> That depends on the PLL design.
> These days there is (hopefully!) a frequency discriminator that checks for
> a valid range (my monitor switches the HV and scanning off, if sync is out
> of range). Else it would blow up.
>
>>And for a strictly fixed-frequency monitor, if I wanted to just use the
>>upper-left portion of the screen, could I just generate h-sync and
>>v-sync pulses twice as fast?
>
No.

> Simpler even, you use the same (correct) H and V frequency, but send the
> info at double speed (double pixel clock) in the first line, and
> wait the other half line time, and send the info in the second line you
> have at double speed, etc, until you run out of lines.
> This assumes your monitor can display those double high frequencies
> (detail). This also shows you need _half_ the number of lines in your
> original! On a 600 line height screen you have only 300 lines for half the
> picture.
>
>
>
>> (This would, of course, mean that I'm
>>sending the "wrong" sync frequencies to a fixed-frequency monitor. I'm
>>not sure whether there any any components that could fail by doing
>>this.)
>
> So no need to do that.

See within.

--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller
First  |  Prev  |  Next  |  Last
Pages: 1 2 3 4 5
Prev: Digital automotive tach circuit?
Next: BDM download cables - compatibility issues.