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From: joseph2k on 8 Nov 2006 01:06
Jan Panteltje wrote:

> On a sunny day (Tue, 07 Nov 2006 12:11:30 GMT) it happened joseph2k
> <quiettechblue(a)yahoo.com> wrote in
> <SJ_3h.1040$6t.318(a)newssvr11.news.prodigy.com>:
>
>>BTW i have a LCD monitor exhibiting the equivalent of burn in now.
>
> There was an interesting thread in comp.ibm.hardware.chips about the
> 'LCD" 'burn in' or storage effect, depending on the system and
> manufacturer it sometimes helps to display white for say a night.
>
>
>>> Line burn in often happened, I have had a TV repair shop too, repaired
>>> thousands (no joking), and line burn in I have seen too.
>>> Even some old scopes (at about 4kV) had line burn in (remember
>>> DG57-34???).
>>
>>I saw line burn in on a scope only once, and only heard reports of it on
>>TV's.
>
> First a correction, I think the tube was DG7-32
> http://members.chello.nl/~h.dijkstra19/page3.html
> It is the small one next to the big radar tube.....
> This was my first oscilloscope 'design' (well I designed the power
> supply), it was a tube oscilloscope, probably 1MHz bandwidth, no trigger,
> just 'sync'. A year later I designed a transistor one, with video output
> transistors in the deflection, real trigger, double timebase, on a printed
> ciruit with RTL logic! But anyways, this DG7-32 burned in in the first
> hour or so...
>
>
>>> composite.
>>>
>>>
>>>>>>V-sync is not nearly so straight forward. Google for NTSC and look
>>>>>>for a thorough explanation of vertical sync; to be worthwhile it will
>>>>>>include
>>>>>>"equalizing pulses". Now there is a can of worms for you.
>>>>
>>>>Please explain equalizing pulses.
>>>
>>>
>>> Glad you asked.
>>> We have to look a 3 different cases in case of sync:
>>>
>>> 1) Composite video (with composite sync).
>>> 2) Composite sync, 'S" input.
>>> 3) Separate H and V sync inputs (as in VGA 9 pole connector, the OP was
>>> talking about originally).
>>>
>>> To start with 3 (simplest) most of the time the computer display is not
>>> interlaced, and H and V can just be simple pulses, there need not even
>>> be a frequency lock (both derived from the same clock etc).
>>> And in case of interlace you need no 'egalisation' in fact.
>> ^equalization
>>See below.
>>
>>>
>>> This brings me to your question in case '1' and '2'.
>>> The original reason for the egalisation pulses is dead simple, and
>>> almost never mentioned. The intention was to have the (interlaced)
>>> receiver sync separator circuit _as_simple_as_possible_.
>>
>>No, it has to do with maintaining h-sync.
>
> Eh, yes and no.
> In the olden days the time constant in the H PLL was really big, so the
> set would just carry on at last freq if bad signal.
> Then VHS came, and it had big timing errors in H due to the head position
> changes, a big jump in H at the end of the frame (and missing lines at the
> head switch-over).
> So then sets got a much shorter timeconstant for H.
> There was a time TV sets had 2 time constants.
>
>
>
>
>>> The egalisation pulses are there to make sure the V integrator capacitor
>>> is charged in such a way that the vertical retrace will start at half a
>>> line (625 / 2 = 312 1/2 in European PAL).
>>>
>>
>>Equalization pulses bent the H sync so that it would be back in place at
>>the
>>end of V sync. They occur on blank lines both before and after the V
>>sync series.
>
>
> Yes I know where they are.
> Let's go a bit deeper:
> If you xor the H with a longer V you get reversed H, but now the H starts
> posive, and trhe differentiator in the sync separator deleivers a
> negatibve pulse, and as we were using the negative pulse it is about 4.7uS
> late. However the H PLL will adjust in few lines.
>
> -- ------------ ------------ --
> | | | | | | |
> | | | | | | |
> -- -- ------------- ---
> || ||
> || ||
> || ||
> position of 'optional' egalisation pulses.
>
>
>>> This system was designed so you could just with a simple differentiator
>>> and integrator split the composite sync.
>>>
>>> .
>>> .
>>> integrator .
>>> neg polarity R . ramp build up
>>> during v sync. comp sync ----------====-------------- V sync .
>>> | |
>>> | === C
>>> | |
>>> | ///
>>> | |\
>>> | differentiator | \
>>> | | | C ___ __| \_____
>>> -----| |---------------- H sync | /
>>> | | | | /
>>> | |/
>>> [ ] R This edge is used (_also_
>>> [ in egalisation pulses!)
>>> |
>>> ///
>>>
>>>
>>> It must again be stressed that the comp sync does not need any
>>> egalisation pulses if the display is not interlaced.
>>> maybe some of you will remember the real start of computing, Motorola
>>> max-board with 6845 CRT controller, you just made comp sync by xoring a
>>> H pulse with a V pulse....... And the TV would be nicely locked.
>>> And that twas even a common clock.
>
>>You forget it only displayed on even fields. It was not until the 6845A
>>that you could even try to use both vertical scans and even then it did
>>not work correctly.
>
> Actually in the above drawing the V ramp is negative of course.....
>
> I would have to climb in the attic, but I had interlace on a Z80 system
> I designed with a 6845, but not sure it was 'A' or not.
>
> Interlace is just a phase relationship between H and V, if you have a
> Lissajous (spelling) display of 2 sine waves on the scope, you can phase
> adjust so the lines do not overlap (pairing it is called).
> The extra pulses cause the V integrator cap to charge a bit different, and
> change the phase where the V
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