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From: Jon Beniston on 13 Mar 2010 15:26 > The common metric for ASICs is to count gates in terms of the > number of transistor in a two input NAND gate (four in CMOS), > and so divide the number of transistors by that number. Usually you divide the combined area of all the cells by the area of the lowest drive strength 2-input NAND. (Similar, but not quite the same, as you take in to account the size of the transistors as well as the number). Jon |