Computer Architecture
in [Hardware]
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How Many Processor Cores Are Enough? Today I read that we're going to get quad-core processors in 2007, and 80-core processors in 5 years. This has got me to wondering where the point of diminishing returns is for processor cores. We've all seen those bench marks in which the same test is run on a system with 128MB of RAM, then 256MB, then 512MB, .... 15 Dec 2006 05:28
Trying to design low level hard disk manipulation program I posted this on comp.lang.asm.x86, alt.os.development, comp.arch, comp.lang.c++ Im working with windows xp professional, NTFS and programming with MASM, c++ (free compiler) or visual basic 6.0 === question 1 Primarily Im trying to design a program that has full control over a hard disk. What it needs to do... 16 Oct 2006 21:16
"Livermore Loops" on x86 Linux I recently downloaded C code for Livermore Loops from http://www.netlib.org/benchmark/livermorec How can compile it for x86 Linux using gcc? ... 19 Jun 2006 23:36
C++: 64 bit performance vs. 32 bit All, Does anyone know how much performance speedup I can expect by using 64 bit C++ / Windows XP 64 bit over the 32 bit versions? Did anyone test this under Visual Studio 2005 or Intel C++ 8.1/9.0 ? My application domain is montecarlo simulations but any test would be great. Regards Lars Schouw ... 14 Mar 2006 13:24
interrupting for overflow and loop termination Are there any CPU architectures which tie the overflow flag to an interrupt, so that programs don't have to put a flag test and conditional branch after each arithmetic operation in order to avoid modular arithmetic? And similarly, are there any architectures which tie the output of a logic function (hardwired or ... 28 Sep 2005 07:35
Intel x86 memory model question The question isn't what is the x86 memory model. If you want to discuss that, you are welcome to join the fray on c.p.t. The question is why can't or why doesn't Intel want to document the x86 memory model since apparently what is in the System Programming Guide is *not* the memory model. I.e. not as far as pro... 14 Sep 2005 08:23
CPU <> Memory chip communication interface Hi, First I would like to program a simple CPU and Memory chip in pascal/delphi. (Maybe a better word for memory chip would be memory controller ?) The CPU and Memory chip communicatie in serial bits with each other. These serial bits could be commands/addressess which the memory chip can understand. I ... 30 Aug 2005 11:32
IBM 360/370 instruction set architecture Hi, Does anyone know any links for the IBM 360/370 instruction set architecture? I've been looking for it for a very looooong time but i've found no good site about it. I just need a list of instructions for 360/370, addressing modes and instruction formats. Please help me Adam ... 10 Jun 2005 20:47
Where is balance? -- Re: Academic priorities >I'd expect smoothness to be understood in college, maybe high school for the truly precious. I think its hard to understand what C infinity really is without a good course in math. OK smoothness, continuity and analyticity are all nice. BUT when do you start teaching people that functions with even C0 are th... 22 May 2005 18:19
The Case For Biquinary I recently acquired an IBM 650 manual, and I was interested to learn that it used a biquinary representation for integers. This is a decimal format, in which five bits represent the values 0-4 or 5-9 and two binary bits select between the upper and lower range of values. (In other biquinary formats, a single bi... 18 Apr 2005 16:39 |