Prev: initialization issues on Spartan-3E after startup
Next: CPLD + MCU SoC from Cypress, free samples too!
From: Antti on 4 Nov 2009 18:04 On Nov 5, 12:58 am, n...(a)puntnl.niks (Nico Coesel) wrote: > austin <aus...(a)xilinx.com> wrote: > >All, > > >I was puzzled that they used a push of the 65nm technology node (to > >60nm). > > >It is a huge investment for a FPGA device company to launch a new > >family, and to launch one with "the old" technology node means that > >the latest technology node is guaranteed to beat you on price, power, > >and/or performance (since 90nm, we do not get to choose all three, we > >are at best a two out of three for a new node). > > >True, S6 is optimized for power (first time we have ever used a low > >power process from a foundry), so bragging about performance is one > >way to shout very loudly "we sure burn a lot more power!" > > >When we asked customers what their number one need was for S6, it was > >"lower the power!" > > >I know that many like to use the latest Spartan node to replace the > >previous Virtex node (lower their bill of materials costs), but > >frankly, S6 was designed for a new markets, and not intended to > >cannibalize Virtex 5 sockets. > > That raises the question: Can we expect to see a new Spartan series > with more speed? > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > "If it doesn't fit, use a bigger hammer!" > -------------------------------------------------------------- i would like to see the spartan with ARM core first Xilinx should have inhouse silicon of it already if they are aiming to release it as planned Antti
From: -jg on 5 Nov 2009 00:25 On Nov 5, 12:04 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > i would like to see the spartan with ARM core first > Xilinx should have inhouse silicon of it already if they are aiming to > release it as planned Triscend revisited ? A key question is not the core, but what memory they put around it ? Plenty of ARM cores out there, that have memory included (they are called Microcontrollers!) - and the choice is growing. -jg
From: Antti on 5 Nov 2009 00:28 On Nov 5, 7:25 am, -jg <jim.granvi...(a)gmail.com> wrote: > On Nov 5, 12:04 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > i would like to see the spartan with ARM core first > > Xilinx should have inhouse silicon of it already if they are aiming to > > release it as planned > > Triscend revisited ? > > A key question is not the core, but what memory they put around it ? > > Plenty of ARM cores out there, that have memory included > (they are called Microcontrollers!) - and the choice is growing. > > -jg well ARM+CPLD is again announced now too, its called PSoC 5 cortex-M3 + small CPLD Antti
From: Jon Beniston on 5 Nov 2009 06:26 >I was puzzled that they used a push of the 65nm technology node (to > 60nm). > It is a huge investment for a FPGA device company to launch a new > family, and to launch one with "the old" technology node means that > the latest technology node is guaranteed to beat you on price, power, > and/or performance (since 90nm, we do not get to choose all three, we > are at best a two out of three for a new node). TSMCs problems at 40nm are pretty well documented. Cheers, Jon
From: David Brown on 5 Nov 2009 08:33 Torfinn Ingolfsen wrote: > Antti wrote: >> Hi >> >> Altera is promising 25% more fabric speed than S6 with their new >> Cyclone IV > > And us hobbyist types are wondering: will Altera give us a _free_ > development environment for Linux this time? > (just in case anyone from Altera drops in here occasionally). There's a beta version available (I haven't tried it - I just noticed it on their web site when wandering about).
First
|
Prev
|
Next
|
Last
Pages: 1 2 3 4 Prev: initialization issues on Spartan-3E after startup Next: CPLD + MCU SoC from Cypress, free samples too! |