DDRé SDRAM configuration
in [FPGA]
|
From: Gladys on 21 Jul 2010 11:51 On 19 juil, 17:08, Gabor <ga...(a)alacron.com> wrote: > The chip you mentioned, MT47H64M16, is 1 gigabit, not 1 gigabyte. You > need 8 of these chips for 1 gigabyte of memory. I don't think you'll > be able > to drive 8 chips with the Spartan 6 MIG controller. Check carefully > in the > customization screens for MIG to see what you can do. > Yes you are right, it's 1Gigabit and there's only 1 memory chip in my implementation, I think in this case I will scale down the image resolution to 3000x2748, then it could fit 9 frames of images. > So sticking to me original idea of a 16-bit wide interface, even if > you > wasted the upper 4 bits you could store and retrieve 600 million > pixels per second at 300 MHz. I would consider running the > interface at a more comfortable 200 MHz which still gives you > a lot of extra bandwidth if all you need is a pixel buffer. > > > What is the speed grade of the MT47H64M16? That would need to > be -3 for the 300 MHz interface. a -5 part would be good enough > for 200 MHz. the speed grade of MT47H64M16 is -3. > > If your pixels are 12 bits and you want to store them in 16-bit wide > memory, concatenate 4 of them to make 48 bits of pixel data > which fit into three 16-bit words. > How to implement this? If I choose the 128bit R/W port configuration, Should I pack 12bits pixel at the host side for the 128bits write data FIFO? > I'm still not convinced you do have memory to waste, but the basic > idea is > to start a new image line on say a 4096-word boundary even though the > actual line width is only 3664. This makes line addressing simpler. > Do > something similar by starting a new frame buffer at a 4096-line > boundary > even though the frame is only 2748 lines. This will mean that > addressing > within a frame buffer is a simpler function of pixel and line > position. > If I do this, each frame of image will take 4096*4096*12= 201,326,592bits, I can olny store 5 image in the SDRAM, which doesn't meet the requirement, In this case, can I store images and meanwhile read them out, the SDRAM will perform as a large FIFO. Also to simplify the logic, I can leave the 4bits unused as I don't need to store as much images as before? Thanks! > > > > > Gladys
From: Gladys on 22 Jul 2010 04:33
On 19 juil, 17:08, Gabor <ga...(a)alacron.com> wrote: > The chip you mentioned, MT47H64M16, is 1 gigabit, not 1 gigabyte. You > need 8 of these chips for 1 gigabyte of memory. I don't think you'll > be able > to drive 8 chips with the Spartan 6 MIG controller. Check carefully > in the > customization screens for MIG to see what you can do. Yes you are right, it's 1Gigabit and there's only 1 memory chip in my implementation. Actually now I just need to store maximum 3 frames of images in the DDR2, so there will be enough memory space for 3664 x 2748 x 12 x 3 = 362472192. > So sticking to me original idea of a 16-bit wide interface, even if > you > wasted the upper 4 bits you could store and retrieve 600 million > pixels per second at 300 MHz. I would consider running the > interface at a more comfortable 200 MHz which still gives you > a lot of extra bandwidth if all you need is a pixel buffer. Do the store and retrieve perform at the same frequency? Shall I slow down the rate of read in the read FIFO of MCB? > What is the speed grade of the MT47H64M16? That would need to > be -3 for the 300 MHz interface. a -5 part would be good enough > for 200 MHz. the speed grade of MT47H64M16 is -3. I just need to write and read about 30 million pixel once, so is 200MHz good enough for the design? > If your pixels are 12 bits and you want to store them in 16-bit wide > memory, concatenate 4 of them to make 48 bits of pixel data > which fit into three 16-bit words. How to implement this? If I choose the 128bit R/W port configuration, Should I pack 12bits pixel at the host side for the 128bits write data FIFO? Also now since I just need to store 3 frames, so I can waste the upper 4 bits, However, I don't understand how does the internal 128bits signal at host side transfered to 16bits signal at the DDR2 side, is the 128bits a set of 8 16 bits? > I'm still not convinced you do have memory to waste, but the basic > idea is > to start a new image line on say a 4096-word boundary even though the > actual line width is only 3664. This makes line addressing simpler. > Do > something similar by starting a new frame buffer at a 4096-line > boundary > even though the frame is only 2748 lines. This will mean that > addressing > within a frame buffer is a simpler function of pixel and line > position. Can I store the 3 images in different bank, for example, frame 1 in bank 1and 2, frame 2 in bank 3 and 4, and so forth. Sorry about my stupid questions, thank you again for your anwsers. |