Derived clock violation in Virtex4
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From: Verictor on 18 Feb 2010 20:18 On Feb 18, 12:51 pm, "maxascent" <maxascent(a)n_o_s_p_a_m.yahoo.co.uk> wrote: > >Verictor pisze: > >> Hi, > > >> I have a V4 with input clock frequency running at 130MHz. This clock > >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is > >> named as "derived_clock" by Synplify. Now the timing report on the > >> input 130MHz is fine (positive slack) but the derived_clock doesn't > >> meet timing. How to contrain that? > > >> Thanks. > > You havent added any clock buffers (BUFG) on the output of the DCM. > > Jon > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com No, I do have inserted IBUFG to input clock and BUFG to the output of the DCM. Just not shown on my post.
From: maxascent on 19 Feb 2010 04:00 You should only need to specify the clock into the DCM in the Synplify constraint file. If your design is not meeting timing then you need to look in the Synplify report and find the problem. Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: Brian Drummond on 19 Feb 2010 06:22 On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehuang(a)gmail.com> wrote: >On Feb 18, 12:51�pm, "maxascent" <maxascent(a)n_o_s_p_a_m.yahoo.co.uk> >wrote: >> >Verictor pisze: >> >> Hi, >> >> >> I have a V4 with input clock frequency running at 130MHz. This clock >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is >> >> named as "derived_clock" by Synplify. Now the timing report on the >> >> input 130MHz is fine (positive slack) but the derived_clock doesn't >> >> meet timing. How to contrain that? >> >> >> Thanks. >> >> You havent added any clock buffers (BUFG) on the output of the DCM. >> >> Jon � � � � >> >> --------------------------------------- � � � � >> Posted throughhttp://www.FPGARelated.com > >No, I do have inserted IBUFG to input clock and BUFG to the output of >the DCM. Just not shown on my post. Then we have to guess that the BUFG has SClkPre as input and SClk as output, since SClk is taken to ClkFB (feedback) on the DCM. Then SClk should be correctly aligned with the DCM input clock, which means there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal). Is that what you are observing? - Brian
From: Verictor on 23 Feb 2010 09:53 On Feb 19, 4:22 am, Brian Drummond <brian_drumm...(a)btconnect.com> wrote: > On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehu...(a)gmail.com> wrote: > >On Feb 18, 12:51 pm, "maxascent" <maxascent(a)n_o_s_p_a_m.yahoo.co.uk> > >wrote: > >> >Verictor pisze: > >> >> Hi, > > >> >> I have a V4 with input clock frequency running at 130MHz. This clock > >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is > >> >> named as "derived_clock" by Synplify. Now the timing report on the > >> >> input 130MHz is fine (positive slack) but the derived_clock doesn't > >> >> meet timing. How to contrain that? > > >> >> Thanks. > > >> You havent added any clock buffers (BUFG) on the output of the DCM. > > >> Jon > > >> --------------------------------------- > >> Posted throughhttp://www.FPGARelated.com > > >No, I do have inserted IBUFG to input clock and BUFG to the output of > >the DCM. Just not shown on my post. > > Then we have to guess that the BUFG has SClkPre as input and SClk as output, > since SClk is taken to ClkFB (feedback) on the DCM. > > Then SClk should be correctly aligned with the DCM input clock, which means > there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal). > Is that what you are observing? > > - Brian- Hide quoted text - > > - Show quoted text - Brian, Your guess of BUFG is exactly right. Also yes, SClk should be aligned with CLKIN, as you pointed out. When you said "observing", I think you mean post-layout simulation? I haven't done that. But I think the alignment should be ok. Thanks,
From: Brian Drummond on 23 Feb 2010 16:30
On Tue, 23 Feb 2010 06:53:08 -0800 (PST), Verictor <stehuang(a)gmail.com> wrote: >On Feb 19, 4:22�am, Brian Drummond <brian_drumm...(a)btconnect.com> >wrote: >> On Thu, 18 Feb 2010 17:18:14 -0800 (PST), Verictor <stehu...(a)gmail.com> wrote: >> >On Feb 18, 12:51�pm, "maxascent" <maxascent(a)n_o_s_p_a_m.yahoo.co.uk> >> >wrote: >> >> >Verictor pisze: >> >> >> Hi, >> >> >> >> I have a V4 with input clock frequency running at 130MHz. This clock >> >> >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is >> >> >> named as "derived_clock" by Synplify. Now the timing report on the >> >> >> input 130MHz is fine (positive slack) but the derived_clock doesn't >> >> >> meet timing. How to contrain that? >> >> >> You havent added any clock buffers (BUFG) on the output of the DCM. >> >No, I do have inserted IBUFG to input clock and BUFG to the output of >> >the DCM. Just not shown on my post. >> Then SClk should be correctly aligned with the DCM input clock, which means >> there will be several ns skew (= the BUFG delay) on SClkPre (the DCM0 signal). >> Is that what you are observing? >Your guess of BUFG is exactly right. Also yes, SClk should be aligned >with CLKIN, as you pointed out. When you said "observing", I think you >mean post-layout simulation? I haven't done that. But I think the >alignment should be ok. I actually meant "observing" because you observed in your original query, you reported the "derived clock" DCM0 signal (skewed as above) didn't meet timing. Since the skew is expected, the question is, what exactly doesn't meet timing? If there is any logic clocked off DCM0 it will probably not meet timing; but there shouldn't be any. DCM0 should only connect to the BUFG and nothing else. - Brian |