Derived clock violation in Virtex4
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From: Verictor on 17 Feb 2010 21:09 Hi, I have a V4 with input clock frequency running at 130MHz. This clock goes into a DCM then CLK0 goes out to other logic. The CLK0 net is named as "derived_clock" by Synplify. Now the timing report on the input 130MHz is fine (positive slack) but the derived_clock doesn't meet timing. How to contrain that? Thanks.
From: maxascent on 18 Feb 2010 04:21 You need to post your code so we can see how you have coded the DCM. Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: Verictor on 18 Feb 2010 11:34 On Feb 18, 2:21 am, "maxascent" <maxascent(a)n_o_s_p_a_m.yahoo.co.uk> wrote: > You need to post your code so we can see how you have coded the DCM. > > Jon > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com Here is it, thanks. DCM_1 : DCM_ADV generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 2, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 7.6921, -- 7.69 for 130MHz CLKOUT_PHASE_SHIFT => "NONE", DCM_PERFORMANCE_MODE => "MAX_SPEED", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, PHASE_SHIFT => 0, STARTUP_WAIT => FALSE ) port map ( CLK0 => SClkPre, -- *****violation here CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, DO => open, DRDY => open, LOCKED => DLL_LOCKED, PSDONE => open, CLKFB => SClk, CLKIN => SClkIn, DADDR => "0000000", DCLK => '0', DEN => '0', DI => "0000000000000000", DWE => '0', PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => MasterRst );
From: Adam Górski on 18 Feb 2010 11:36 Verictor pisze: > Hi, > > I have a V4 with input clock frequency running at 130MHz. This clock > goes into a DCM then CLK0 goes out to other logic. The CLK0 net is > named as "derived_clock" by Synplify. Now the timing report on the > input 130MHz is fine (positive slack) but the derived_clock doesn't > meet timing. How to contrain that? > > Thanks. Hi, If incoming (external ) clock is used only to drive DCM, you have problem with your design. In different words your logic is too slow. Anyway you can find everything in timing report. I don't know xilinx tools to well but clock coming from DCM should be constrained automatically. Correct me if I'm wrong Adam
From: maxascent on 18 Feb 2010 14:51
>Verictor pisze: >> Hi, >> >> I have a V4 with input clock frequency running at 130MHz. This clock >> goes into a DCM then CLK0 goes out to other logic. The CLK0 net is >> named as "derived_clock" by Synplify. Now the timing report on the >> input 130MHz is fine (positive slack) but the derived_clock doesn't >> meet timing. How to contrain that? >> >> Thanks. > You havent added any clock buffers (BUFG) on the output of the DCM. Jon --------------------------------------- Posted through http://www.FPGARelated.com |