Unpredictable design
in [FPGA]
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From: de4 on 17 Feb 2010 18:55 Hello ! I have a very big problem. I created a simple procesor and on simulation it works fine, on step mode it works fine but when it is running on full speed of clock it got crazy... :( It should execute instruction i order 0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and it executes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 or 0.1 or sometimes it is as it should. Sometimes it stops suddenly executing or executing too much. It is written in VHDL on Spartan 3A. It is too big to show it here but maybe some experts will be able to tell me what is going on... I have constraints like this in UCF file : NET "Clock" LOC = C10; NET "Clock" IOSTANDARD = LVCMOS33; NET "Clock" PERIOD = 62.5ns HIGH 50%; NET "Reset" LOC = H4; NET "Reset" IOSTANDARD = LVCMOS33; NET "TX" LOC = B3; NET "TX" IOSTANDARD = LVCMOS33; NET "RX" LOC = A3; NET "RX" IOSTANDARD = LVCMOS33; are there any other constraint useful for me ? Can it be constraint fault ? Or it must be design problem ? Or something else ? 16Mhz clock is connected to FPGA. It works OK using step by step mode but on full speed it's stragne bevahior... I really need help, I trying to solve it for three days and nothing... Thank you all for any answers... --------------------------------------- Posted through http://www.FPGARelated.com
From: Symon on 17 Feb 2010 19:04 On 2/17/2010 11:55 PM, de4 wrote: > works fine, on step mode it works fine but when it is running on full speed > of clock it got crazy... > NET "Clock" PERIOD = 62.5ns HIGH 50%; > What is 'step mode' exactly? Your clock is relatively slow. So, your problem is probably something to do with clock skew. Is your clock on a GBUF? Does your clock connect to anything other than a dedicated clock input of the FPGAs innards? HTH Syms.
From: johnp on 17 Feb 2010 20:36 On Feb 17, 3:55 pm, "de4" <de4(a)n_o_s_p_a_m.poczta.onet.pl> wrote: > Hello ! > > I have a very big problem. I created a simple procesor and on simulation it > works fine, on step mode it works fine but when it is running on full speed > of clock it got crazy... :( It should execute instruction i order > 0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and it > executes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 or > 0.1 or sometimes it is as it should. Sometimes it stops suddenly executing > or executing too much. It is written in VHDL on Spartan 3A. It is too big > to show it here but maybe some experts will be able to tell me what is > going on... I have constraints like this in UCF file : > > NET "Clock" LOC = C10; > NET "Clock" IOSTANDARD = LVCMOS33; > NET "Clock" PERIOD = 62.5ns HIGH 50%; > NET "Reset" LOC = H4; > NET "Reset" IOSTANDARD = LVCMOS33; > NET "TX" LOC = B3; > NET "TX" IOSTANDARD = LVCMOS33; > NET "RX" LOC = A3; > NET "RX" IOSTANDARD = LVCMOS33; > > are there any other constraint useful for me ? Can it be constraint fault ? > Or it must be design problem ? Or something else ? 16Mhz clock is > connected to FPGA. It works OK using step by step mode but on full speed > it's stragne bevahior... I really need help, I trying to solve it for three > days and nothing... > > Thank you all for any answers... > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com You don't mention if the design passes P&R with no timing errors. Simply specifying constraints doesn't mean they are actually met. John Providenza
From: de4 on 18 Feb 2010 03:04 I'm bigginner so I was trying to verify if my work actually works in FPGA. So as clock of whole system I used FSM controled by push button. When I push the button it gave one clock cycle and because that processor gone to next state - this is what I meant saying 'step mode'. I have written software that reads all registers and memory and sending do computer. And there everything looks ok... Sorry but I don;t know what is GBUF ? I will find it out... My clock isn't comnected to anything else then to FPGA ( I have Avnet Sparatan 3A board) And about constraints in Map messages I have only : (only infos) MapLib:562 - No environment variables are currently set. MapLib:159 - Net Timing constraints on signal Clock are pushed forward through input buffer. LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. It doesn't tell me a lot :( Timing messages Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. And in detailed Post-PAR Static Timing Report is written All constraints were met. What Can I check more ? --------------------------------------- Posted through http://www.FPGARelated.com
From: Brian Drummond on 18 Feb 2010 05:42 On Wed, 17 Feb 2010 17:55:07 -0600, "de4" <de4(a)n_o_s_p_a_m.poczta.onet.pl> wrote: >Hello ! > >I have a very big problem. I created a simple procesor and on simulation it >works fine, on step mode it works fine but when it is running on full speed >of clock it got crazy... : >are there any other constraint useful for me ? Can it be constraint fault ? >Or it must be design problem ? Or something else ? 16Mhz clock is >connected to FPGA. 16MHz is slow enough that problems meeting timing are unlikely. Is the processor accessing any memory external to the FPGA, or just thu internal BRAMs? External memory is a likely source of timing problems. Check for any inputs to the processor that aren't themselves clocked by the same clock, and eliminate them (by reclocking them from the CPU clock. - Brian
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