Digital processing of analog TV broadcast
in [Design]
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From: linnix on 27 Nov 2006 14:17 a7yvm109gf5d1(a)netzero.com wrote: > Is there any reason you are re-inventing the wheel? I second this. Unless you are doing some additional processings, which would require external memories anyway. > > Averlogic AL250 > + > Philips SAA7111 (or is that NXP?) > > Total cost about 30$. Add $10 more for a graphic chip (VGA output).
From: a7yvm109gf5d1 on 27 Nov 2006 14:23 linnix wrote: > a7yvm109gf5d1(a)netzero.com wrote: > > Is there any reason you are re-inventing the wheel? > > I second this. Unless you are doing some additional processings, which > would require external memories anyway. > > > > > Averlogic AL250 > > + > > Philips SAA7111 (or is that NXP?) > > > > Total cost about 30$. > > Add $10 more for a graphic chip (VGA output). What are you talking about? That's what the AL250 does...
From: linnix on 27 Nov 2006 14:49 a7yvm109gf5d1(a)netzero.com wrote: > linnix wrote: > > a7yvm109gf5d1(a)netzero.com wrote: > > > Is there any reason you are re-inventing the wheel? > > > > I second this. Unless you are doing some additional processings, which > > would require external memories anyway. > > > > > > > > Averlogic AL250 > > > + > > > Philips SAA7111 (or is that NXP?) > > > > > > Total cost about 30$. > > > > Add $10 more for a graphic chip (VGA output). > > What are you talking about? That's what the AL250 does... Without looking at the spec, I though that's a micro. But in this case, what do you need the SAA7111 for?
From: a7yvm109gf5d1 on 27 Nov 2006 16:42 linnix wrote: > a7yvm109gf5d1(a)netzero.com wrote: > > linnix wrote: > > > a7yvm109gf5d1(a)netzero.com wrote: > > > > Is there any reason you are re-inventing the wheel? > > > > > > I second this. Unless you are doing some additional processings, which > > > would require external memories anyway. > > > > > > > > > > > Averlogic AL250 > > > > + > > > > Philips SAA7111 (or is that NXP?) > > > > > > > > Total cost about 30$. > > > > > > Add $10 more for a graphic chip (VGA output). > > > > What are you talking about? That's what the AL250 does... > > Without looking at the spec, I though that's a micro. How about looking at the specs? > But in this case, what do you need the SAA7111 for? RTFDS.
From: sp_mclaugh on 27 Nov 2006 17:39
panteltje(a)yahoo.com wrote: > p_mclaugh(a)yahoo.com schreef: > > > Hello, > > > > I'm current designing a device which will digitally convert an analog > > (NTSC) signal to RGB (for use in VGA). I have some questions at the > > bottom of this post. The system design consists of: > > > > - 50 MHz FPGA > > - 50 MSPS 10-bit ADC with video clamping > > - Matching DAC > > - Baseband NTSC composite video source > > - VGA monitor > FPGA board? I'm using a Xilinx Spartan 3 running on a Digilent starter board. At this point, the ADC and DAC will probably be mounted on a seperate breadboard (or PCB, if I feel like outsourcing it). > > The FPGA includes the following sub-blocks > > > > - Polyphase resampler - converts sampled data to 4 * color sub carrier > > frequency (I think this is the correct term, but I'm not sure. I'm > > basically interpolating and then decimating by integer factors) > > mm Ha, that's what I said... I've never done one of these before. The name sounds intimidating, but I don't think it'll be too bad. > > - Low pass filters - I plan on using windowed sinc (FIR) filters for > > everything, unless there is a compelling reason not to > > OK > > > - Numerically controlled oscillator - I will store a table with a > > quarter cycle of a sinusoid, and use trig properties to calculate the > > rest. The index will be N-bits long, and the table will have > > significantly less than 2^N entries. Only the most significant bits of > > the index will be used, and the lower bits will actually be used for > > interpolation (this idea isn't originally mine). > I multiplied the 50MHz FPGA clock to 200MHz (DCM), this gives > quadrature signals at 200MHz.... I've never used the DCM before, but I just downloaded a Xilinx appnote, which I'm reading now. > > - Digital PLL or digital Costas loop - Any advice as to which to use? > > Needed to lock onto color burst to generate reference color subcarrier. > > I plan on using TWO seperate PLL's, since the chroma subcarrier is > > phase-inverted on each line. Each PLL will be updated alternately, > > every other color burst. This will minimize tracking requirements, I > > think. > I found that tricky, so for PAL I used an external Xtal 4.43 (or 8.86 > MHz). > :-) I'm probably going to do some Matlab simulation first, to make sure I get it right. This is mostly a learning project, so I'm going to try to do it all on the FPGA (just out of stubbornness). > > - 2D adaptive comb filter - takes advantage of the fact that the chroma > > subcarrier is phase inverted on each sucessive line to allow good > > seperation of luminance and chrominance. Since the data has been > > resampled to 4 * Fsc, there will be a constant number of samples per > > line, and the pixels will "line up", making the comb filter easier to > > implement. > > > - QAM demodulator - Uses the PLL or Costas loop reference color > > subcarrier to demodulate the chroma signal. Needs only multiplier(s) > > and low pass filters. I'm going to use narrowband color and demodulate > > I and Q with 0.5 MHz bandwidth each. > > > > - Sync detector > > This will depend on how accurate you can get subcarrier lock. > With a 50 MHz clock you have a tick every 20 nS, for NTSC period time > is > some 300 ns? (an estimate, I am in PAL land) The NTSC subcarrier frequency is 3.579545 MHz, so 279.4 ns (pretty close). I was going to just sample as fast as I can (every 20 ns), and use the polyphase resampler (upconvert, interpolate w/ FIR filter, and decimate). Then demodulate by using two multipliers (mult by sin/cos) and two low-pass filters to remove the double-freqency terms. > so and you want to sample 2 > times in a period, your sample target: > > I Q > > . * . > . .* * . > . * . * . > . _____ *______ . ____________________ . _______________________ > * . . > . . > . > > 300ns > <-----------------------------------------> > | | > | sample Q sample Q > | | | | > sample I | sample I | > ------> 75ns | -----> 225ns | > | | > ------------------> 150ns ----> 300ns > > > Using the 50 MHz clock with 20 ns resolution will never give you the > exact sample point. > With a 200 MHz clock you have 5 ns resolution (should be enough), with > a 200 MHz 4 phase > clock 1.25 ns resolution. > > This right? This is why I went to 200 MHz. > And a few other reasons too. Hmm, I think you're using a different QAM demodulation method than I am. I'll have to break out my book and get back to you. > > - Matrix to convert from (Y, I, V) to (R, G, B) > > That is the easy part, although many standards exist :-) > (ask me if you want to know more, I have tried some...). Yes, this part will be a relief. Oops, I think I meant to write (Y, I, Q). > > - Video buffer at 640x480. Each time a field is digitised, every other > > line of the buffer will be updated. The VGA output will run at 60 Hz, > > giving the same interlaced appearance as a regular TV. There may be > > better ways to do this, but this is simple and easy. I'd rather not > > deal with motion compensation. > > Maybe there is no need for a full frame store, unless you want > to make a time base corrector that can handle asyc input sources, > and sync these to some reference. You're completely right. I just happened to already have a Xilinx module which reads from a frame store and handles the VGA generation. If I didn't already have this made and working, I would do things differently. > I did the line doubler (this is called a line doubler) by simply > storing a line in FPGA block RAM, those are dual port RAMS, and > reading it out at double speed. > Thats is all. > So each line is repeated twice. I was going to do this, but I can't remember why I ended up deciding not to... I will consider doing that rather than updating every other line. Either way should be about the same amount of work, I think. > That way 15625 Hz becomes 31250 Hz, nice for a VGA monitor, > the 50 (or 60 Hz in your case) stays the same. > You do not even have to sync that clock. > I used a 2x PLL on H to get H sync for the VGA. > Watch out for jitter and lock in range, especially with VHS as input. That is definitely convenient. Again though, I'm just viewing the VGA module as a "black box" - I just write to the frame buffer and forget about it. Of course, I still do have to have a 2x synchronization between the composite input and VGA output, or weird video will occur during motion. I might just accept this for now, and make a tunable VGA module down the line. > Long time ago I tried all this.... Digilentinc digilab2 Spartan2. > Hope I remembered it right. Yep, I'm using nearly the same thing (Digilent Spartan 3). > Analog is better? Looks like it! > LOL Haha, I think you're probably right. But once I get this basic version working, there is a whole lot of room for improvement, which could surpass analog (ie, a 3d adaptive comb filter isn't possible with analog - or surely isn't practical). Thanks for the help, I'll try to understand your IQ demodulation and how to use Xilinx's DCM. However, since I'm sampling way faster than the Nyquist rate (20ns vs 279ns), shouldn't my method work (synchronous demodulation)? Like I said, I'm new to this. |