Digital processing of analog TV broadcast
in [Design]
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From: Kevin G. Rhoads on 29 Nov 2006 13:12 > I've never done >any surface mount soldering before. I did read about a way to use >solder paste and reflow in a toaster oven, but it'll probably be >trickier than it sounds. For small lots and prototyping the techs here (Dartmouth Physics Dept) find the solder paste is more problematic than using rosin-core wire solder and a fine iron (lead containing solder only). There is one fancy soldering station with capability for dealing with paste, but the paste has shelf-life problems, and old paste is very problematic. Of course, using an iron only works for the surface mount versions where exposed metal is available: SO-8, discretes down to 0508, 0406, (pads deliberately oversized to expose metal) and a little bit of the MSOP stuff. YMMV
From: sp_mclaugh on 29 Nov 2006 21:52 a7yvm109gf5d1(a)netzero.com wrote: > OK, sounds good, but what's the point of having IP on something that > already exists as an ASIC? You won't make a competitive consumer > product that way. I've seen industrial scan doublers for 2000$ OTOH. True, the commercial market has a lot more potential for custom low-run designs. However, it'll be awhile before I'm comfortable marketing any type of design - whether targetted towards the consumer or commercial market. This is strictly a learning project. I'm at minimum a few years off from being able to design this type of thing in an economical manner - at least on my own. There are many broad fields that I am inexperienced in (ie PCB design). However, I do plan on going into DSP and mixed-signal work, so I think this is a good project to use to become familiar with various techniques.
From: sp_mclaugh on 29 Nov 2006 21:55 panteltje(a)yahoo.com wrote: > You may want ot read this, note 2.5ns in the late sixties and > seventies: > http://www.labguysworld.com/Museum014.htm > Fun for me as I worked with that stuff. Very impressive, I gave the site a read. I'm sure that I couldn't do this with the technology from that time period ! Even now, it's going to be difficult. At least I don't have to deal with any time base corrections - I'm just going to use a broadcast video source. Sean
From: sp_mclaugh on 29 Nov 2006 22:18 Ancient_Hacker wrote: > Whew, quite a challenge. Is there some good reason you're doing this > the hard way? The quick answer is... no. It's more of an exercise than a practical design. > Doing it digitally is a bit challenging as you need rather precise > phase lock to the 3.5xx subcarrier and differential phase with gain > tracking. See, I'm still trying to understand why the needed level of precision is difficult to attain. In my case, I'm oversampling by quite a bit (50 MSPS for a ~3.5 MHz signal). My sampling clock comes directly from the FPGA clock - fixed and stable. It is free-running, and bears no relation to the hsync or color subcarrier timing. I regenerate the chroma subcarrier using a numerically controlled oscillator, which generates two outputs 90 degrees out of phase. The NCO is digitally phase locked to the color burst. I seperate the chroma from the luminance using a comb filter (2d adaptive). Then I just do coherent demodulation - multiply the chrominance by the outputs of my numerically controlled oscillator, and low-pass filter. This gives I and Q. Where, specifically, do I have to worry most about the precision of the devices I'm using? Is it that difficult to lock the DPLL to the color burst? Am I missing some huge concept (it's quite likely)? Kevin G. Rhoads wrote: > For small lots and prototyping the techs here (Dartmouth Physics Dept) > find the solder paste is more problematic than using rosin-core wire > solder and a fine iron (lead containing solder only). There is one > fancy soldering station with capability for dealing with paste, but > the paste has shelf-life problems, and old paste is very problematic. I'll see if I can find a fine soldering iron in one of our labs. However, my hand isn't all that steady to begin with, so we'll see...!
From: Frank Raffaeli on 30 Nov 2006 04:26
On Nov 29, 10:18 pm, sp_mcla...(a)yahoo.com wrote: > Ancient_Hacker wrote: > > Whew, quite a challenge. Is there some good reason you're doing this > > the hard way?The quick answer is... no. It's more of an exercise than a practical > design. > > > Doing it digitally is a bit challenging as you need rather precise > > phase lock to the 3.5xx subcarrier and differential phase with gain > > tracking.See, I'm still trying to understand why the needed level of precision > is difficult to attain. In my case, I'm oversampling by quite a bit (50 > MSPS for a ~3.5 MHz signal). My sampling clock comes directly from the > FPGA clock - fixed and stable. It is free-running, and bears no > relation to the hsync or color subcarrier timing. > > I regenerate the chroma subcarrier using a numerically controlled > oscillator, which generates two outputs 90 degrees out of phase. The > NCO is digitally phase locked to the color burst. I seperate the chroma > from the luminance using a comb filter (2d adaptive). Then I just do > coherent demodulation - multiply the chrominance by the outputs of my > numerically controlled oscillator, and low-pass filter. This gives I > and Q. > > Where, specifically, do I have to worry most about the precision of the > devices I'm using? Is it that difficult to lock the DPLL to the color > burst? Am I missing some huge concept (it's quite likely)? > I don't see any major holes in your reasoning. Your reference clock is something to pick with care. 50 MSPS is enough for video or direct IF processing (presuming IF is band-limited, as in the case with a tuner's SAW filter output). In your case (M NTSC), a commonly used I.F. is centered at 44 MHz, with the PIF at 45.75 and SIF at 41.25. Zarlink Semi uses a 20.45 MHz reference (multiplied by 2x for DSP), Micronas uses 18.432 MHz, others use 27 Mhz. Each has advantages and drawbacks. If you want to plan ahead for the direct I.F. demod I would suggest carefully plotting out the sampling components and their aliases. Later you might want to add PAL, SECAM, ATSC and DVB-T. It's very important to make sure your sampling reference is low-jitter (low SSB phase noise oscillator) and that you don't use the FPGA's internal PLL to multiply it for sampling (DSP clock is ok) but you will need a FIFO or some way to cross from clean to dirty clocking boundary. The reason a low phase-noise sampling is important is the chroma domod is very senitive to errors and this will show up in the video as chroma noise and color streaking. One other recommendation: For the filtering, you may eventually want to consider a combination of other topologies instead of a (symetric) FIR: 1) Group-delay compensated IIR - for video / I.F. filtering: it's more economical. 2) CIC - differentiator structure followed by a resonator (integrator) (See Kuc Introduction to Digital Signal Processing) Forget the easy way - your approach, properly implemented, will yield the best result. The hard part is the Audio - are you intending to demodulate BTSC stereo? I recommend doing the video first. Regards, Frank Raffaeli http://www.aomwireless.com/ |