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From: Jan Panteltje on 10 Dec 2006 04:54
On a sunny day (9 Dec 2006 19:23:53 -0800) it happened sp_mclaugh(a)yahoo.com
wrote in <1165721033.536198.147350(a)l12g2000cwl.googlegroups.com>:

>Jan Panteltje wrote:
>
>> Yes and no, the oscillator is a junction FET with 8.83 Mhz xtal, but
>> then goes into a Schmitt trigger and the square wave enters the FPGA.
>
>I see.
>
>> I made a nice PAL quadrature encoder some time ago (years) with CMOS 4053
>> switches (the idea I got from some Elector article) could dig
>> up that diagram, using a 2 inverter TTL oscillator at 8.83.
>> In the same way you can either sample via a AD, or use drive CMOS
>> switches to sample, here is some circuit that is analog, but digital anyways :-)
>
>Wow, pretty neat idea. BTW, do you do the ASCII art by hand or with a
>program? Looks pretty good, I'd be too lazy to do that much by hand.
>:-)

No, by hand, but i have a good editor (not emacs ;-) ).
Actually about the square wave at top left that being is sampled, imagine chrominance,
with burst:


|||||||||| |||||
|||---||||||||||-----|||--||||| etc
|||||||||| |||||
burst color burst color


If you put this chroma into a limiting amp, the burst will come out like that square wave.
The sample pulse to the 4016 CMOS switch is gated by the burst gate, that way you lock to
the rising edge of the burst (in fact the zero crossing).
It also works if you do not clip, but then you sample in a sinewave, so less gain in the PLL
loop.

This brings me to a point i do not see anywhere in your idea:
In a normal TV signal the burst (and chroma) amplitude) can vary widely (relative to the sync
amplitude).
For this reason there always is a 'chroma AGC', in the TDA3560.pdf you will find an AGC
circuit that will support burst up from 50 mV or so (versus 300mV normal).
If you digitise composite you may in some circumstances have only 50 mV pp burst, so
if you have 8 bits for a full 1V video signal, 1/20 of the range is not much.
Such a small burst amplitude sampled at 3 x Fc (or 4 x Fc) with only a few bits depth
does not seem to help accuracy a lot?
1 / 256 = 3.9mv step, so 50 / 3.9 = 12.8 steps = 4 bits (0-15).

Am I wrong?


>> I dunno, lookup TDA3560.pdf, an analog PAL demodulator chip, look at the
>> application diagram.
>> _Worst case_ 5 degrees error, RGB out, note the delay line.
>
>I didn't do out the exact calculations, but I seem to recall that would
>mean you'd introduce Sin[5 deg] * 100% = 8.7% of I into Q and
>vice-versa. Don't take my word for it though. Maybe I'll dig up a book
>or do it out myself if I remember to. Beyond this calculation, I think
>it's up to the physiology people to explain what the average human
>perceives as more offensive...

that is worst case (400Hz fc deviation, temp, what not).

>> So maybe after you do the NTSC thingy you can start with the PAL design ;-)
>
>Haha, perhaps I could. Actually though, I think my next project will be
>decoding broadcast HDTV (maybe 8-VSB, though I don't know yet, it'll be
>awhile).

Oops. Next we will be talking Viterbi, have not 100% hacked that myself,
HDTV here used DVB-S2.
DVB-S2 is a whole different beast altogether we have here:
http://en.wikipedia.org/wiki/DVB-S
note the link to FEC coding:
http://en.wikipedia.org/wiki/BCH_code
it is to .7 dB of the Shanon limit!

>One other question for you. I've dediced that I'm definitely using the
>Philips TDA8708A that you recommended. I have enough to deal with on
>the digital side, without worrying about DC restoration (video
>clamping), auto gain control, and sample-and-hold. The TDA8708A seems
>like a prototyper's dream come true.

IIRC the max sampling is about 32 Mhz, I did see your question about a 50m/s
ADC in comp.arch.fpga.


>I have two questions though.
>1 - Did you use the recommended 5th order Chebyshev filter that is
>shown in the TDA8708A datasheet? It's on page 17, and consists of 2
>resistors, 2 inductors, and 5 caps. Looks pretty easy, being a total of
>only 9 passives. They also show an alternate schematic on p18, but the
>frequency response isn't as flat in the passband.

I used the adapted Chebyshev, had to look up my diagram, and it takes
about 2 cm^2 boardspace with the inductors vertical.
Note that pad capacitance may require you to use a lower value for the 12pF,
maybe 10pF.


>2 - What did you do to generate the required clamping pulses? ie, pins
>26 (black level sync pulse) or pin 27 (sync level sync pulse)?

Well, the original design (I did several tests) had syc separator with a
LM1881, and then the sample pulses were generated in FPGA.
That LM did not work very well, so I then just did not use the gain and sampling
circuit in the TDA8708, and simply made a bottom sync diode clamp and
fed the video directly into the low-pass.
Then I did the sync-slicing and 2H PLL in verilog.

>I think
>you only have to use one of them. Did you generate the pulses digitally
>in the Spartan, or use a separate analog sync extractor? I figure that
>I already have to look for the hsync pulses in the FPGA, so I could
>probably do it that way... But it might be more robust to use a
>dedicated chip.

Just answered that i think.

>BTW, I'm also planning on making a digital storage oscilloscope down
>the line. Would the TDA8708A function as a regular ADC (no clamping) if
>those two pins were just tied to ground? It's still the best and
>cheapest DIP ADC I can find. I got it for like 6 bucks.

Just answered that too :-)
Yes but it has some weird voltage level for digital zero, not sure how
stable that really is, used a 10 turn trimmer :-)
You could make a J FET diff amp and interface directly to pin 20 for a scope.
128 steps up and down, V pos potmeter on front replaces my trimpot.


>Any other peculiarities to worry about with the TDA8708A, or any
>warnings?

Yes, I think they no longer make it :-)
I have 2, I can tell you were I got these (www.DIL.nl Rotterdam Netherlands).

>I'm planning to breadboard it, so I hope I don't have
>problems with inadequate grounding... I've heard of people using
>breadboards and getting huge spikes on their analog signal whenever the
>clock strikes. I think they were using a different ADC, but...

Oh, well, ftp://panteltje.com/pub/2h/alles.jpg
Note the empty LM1881 socket, the TDA is on the top left board, you
can see the filter too, sorry for out of focus, fixed focus camera,
could not get closer.
Also note the LCD and card-reader slot.
That was for PAY TV you know ;-), ran some sort of DES brute force
in the Spartan.
Of course not any longer now it is possibly illegal.



>Ooh, that reminds me, time to order a high density DSUB header and an
>RCA header...

Yea.
Lots of headers.
From: sp_mclaugh on 10 Dec 2006 13:08
Jan Panteltje wrote:

> This brings me to a point i do not see anywhere in your idea:
> In a normal TV signal the burst (and chroma) amplitude) can vary widely (relative to the sync
> amplitude).
> For this reason there always is a 'chroma AGC', in the TDA3560.pdf you will find an AGC
> circuit that will support burst up from 50 mV or so (versus 300mV normal).
> If you digitise composite you may in some circumstances have only 50 mV pp burst, so
> if you have 8 bits for a full 1V video signal, 1/20 of the range is not much.
> Such a small burst amplitude sampled at 3 x Fc (or 4 x Fc) with only a few bits depth
> does not seem to help accuracy a lot?
> 1 / 256 = 3.9mv step, so 50 / 3.9 = 12.8 steps = 4 bits (0-15).
>
> Am I wrong?

I think that is the weakest point in my design. Like you said, the
chroma is contained within only 12.8 LSB's of the ADC. I'm just hoping
for the best. I'll simulate whatever DPLL I decide on before I
implement it in hardware. Probably using Mathematica, though I really
should brush up on my Matlab skills. I wonder if some type of
regression routine could be implemented (within reasonable real estate
space) to find the optimum frequency and phase of the burst, completely
bypassing the DPLL... Then just use direct digital synthesis (if that's
the correct term) to generate the subcarrier until the next horizontal
line. I'll have to experiment.

> >you'd introduce Sin[5 deg] * 100% = 8.7% of I into Q and

> that is worst case (400Hz fc deviation, temp, what not).

Yes, true. It's probably not nearly that bad. I guess this is actually
the same issue that I'm asking about in the comp.arch.fpga group - I
want a very low jitter clock. Though, I wonder if my design is more
sensitive to clock jitter, since I need to use a DPLL on the chroma
burst, whereas you can just read in I, Q, I, Q after you've seperated
luminance from chrominance.

Which brings me to another question... You used the TDA3560 to generate
your ADC sampling clock, correct? With the varicap for fine tuning. Did
you use any of it's other features, or just the clock? I couldn't find
where it outputs the chroma-locked clock (I see that it has one, but is
it just internal?). But it seems to be capable of doing the entire
demodulation process - all the way to RGB.

> Oops. Next we will be talking Viterbi, have not 100% hacked that myself,
> HDTV here used DVB-S2.
> DVB-S2 is a whole different beast altogether we have here:
> http://en.wikipedia.org/wiki/DVB-S
> note the link to FEC coding:
> http://en.wikipedia.org/wiki/BCH_code
> it is to .7 dB of the Shanon limit!

This should make for quite a challenging project! But then again, it
would be nice to get proficient with something like that before the
market is mature. Could be some nice opportunities.

> IIRC the max sampling is about 32 Mhz, I did see your question about a 50m/s
> ADC in comp.arch.fpga.

Yes, I just realized that too! I should've ordered either 32 MHz or 64
MHz crystal oscillators! But I have a whole bunch of 50 MHz 8-DIPs, so
maybe I'll just divide one down to 25 MHz in the FPGA. Or I'll just buy
some more oscillators, it's not like they're expensive. I seem to be
getting mixed up with one of the projects you described earlier -
something about using a 200 MHz sampling clock. But surely that wasn't
with the TDA8708A, right?

BTW, it actually worked out pretty well splitting my questions into
sci.electronics.design and comp.arch.fpga. I've gotten really good
responses from both (many from yourself).

> I used the adapted Chebyshev, had to look up my diagram, and it takes
> about 2 cm^2 boardspace with the inductors vertical.
> Note that pad capacitance may require you to use a lower value for the 12pF,
> maybe 10pF.

Good to know.

> >2 - What did you do to generate the required clamping pulses? ie, pins
> >26 (black level sync pulse) or pin 27 (sync level sync pulse)?
>
> Well, the original design (I did several tests) had syc separator with a
> LM1881, and then the sample pulses were generated in FPGA.
> That LM did not work very well, so I then just did not use the gain and sampling
> circuit in the TDA8708, and simply made a bottom sync diode clamp and
> fed the video directly into the low-pass.
> Then I did the sync-slicing and 2H PLL in verilog.


> Just answered that too :-)
> Yes but it has some weird voltage level for digital zero, not sure how
> stable that really is, used a 10 turn trimmer :-)
> You could make a J FET diff amp and interface directly to pin 20 for a scope.
> 128 steps up and down, V pos potmeter on front replaces my trimpot.

That sounds like a good idea. Actually, I'd probably want to put a
front-end which changes both offset *and* gain. That way the user could
select the full-swing voltage range, and analyze either large or small
signals, with good precision for both.

> Yes, I think they no longer make it :-)

Haha, so that's why the Mouser and Digikey didn't have it. Doesn't seem
too surprising, 12 years would be a long lifespan for a video IC.

> Oh, well, ftp://panteltje.com/pub/2h/alles.jpg
> Note the empty LM1881 socket, the TDA is on the top left board, you
> can see the filter too, sorry for out of focus, fixed focus camera,
> could not get closer.
> Also note the LCD and card-reader slot.

Seems like we've been playing with the same toys. I actually just did a
small demo project with a Panasonic card reader that we got for about
$4. Nothing to do with TV though.

> That was for PAY TV you know ;-), ran some sort of DES brute force
> in the Spartan.
> Of course not any longer now it is possibly illegal.

I've thought about trying some descrambling. The descrambling web sites
all say "for educational purposes only", though I'd probably be the
only one taking that seriously! I don't think I'd attempt anything with
DES, but just something simple like supressed sync (maybe SSAVI). I
don't plan on doing this soon, though. If at all.

> Yea.
> Lots of headers.

I'm a bit torn between spending $6-$10 on a VGA to DIP header (could
use solderless breadboard), or spending the time to solder up my own
solution... Same goes for the RCA header and IDC ribbons. I know I
could do the whole breadboard in a few hours, but being lazy, I think
I'm just going to pay the money. Plus my work tends to be rather messy
(OTOH, the picture you sent is quite clean looking). If I was
*smarter*, I'd have realized that I'm nearing the $50 range, where I
could just mail-order a PCB. But I'm not. :-)

Thanks,

Sean

From: Jan Panteltje on 10 Dec 2006 13:49
On a sunny day (10 Dec 2006 10:08:02 -0800) it happened sp_mclaugh(a)yahoo.com
wrote in <1165774082.635298.65020(a)j44g2000cwa.googlegroups.com>:

>Which brings me to another question... You used the TDA3560 to generate
>your ADC sampling clock, correct? With the varicap for fine tuning. Did
>you use any of it's other features, or just the clock? I couldn't find
>where it outputs the chroma-locked clock (I see that it has one, but is
>it just internal?). But it seems to be capable of doing the entire
>demodulation process - all the way to RGB.

Yes, anyways it is a PAL chip.
You can grab the clock with any high impedance from the Xtal at pin 20.

>Yes, I just realized that too! I should've ordered either 32 MHz or 64
>MHz crystal oscillators! But I have a whole bunch of 50 MHz 8-DIPs, so
>maybe I'll just divide one down to 25 MHz in the FPGA. Or I'll just buy
>some more oscillators, it's not like they're expensive. I seem to be
>getting mixed up with one of the projects you described earlier -
>something about using a 200 MHz sampling clock. But surely that wasn't
>with the TDA8708A, right?

No, that was to generate PAL quadrature :-)

>I'm a bit torn between spending $6-$10 on a VGA to DIP header (could
>use solderless breadboard),

Not sure wat you want to do here, I use a 15 pol D connector for RGB
to the Samsung Syncmaster monitor, it has 3 BNC connectors (apart from
the normal VGA) and I can select video input2 from the monitor front.
Very convenient.
I thought you were referring to the 90 degrees headers that connect to
the digilab board.

>or spending the time to solder up my own
>solution... Same goes for the RCA header and IDC ribbons. I know I
>could do the whole breadboard in a few hours, but being lazy, I think
>I'm just going to pay the money. Plus my work tends to be rather messy
>(OTOH, the picture you sent is quite clean looking).

Eh, wait till yo usee the wiring on the back :-) It is done with split
flat cable.

>If I was
>*smarter*, I'd have realized that I'm nearing the $50 range, where I
>could just mail-order a PCB. But I'm not. :-)
>
>Thanks,
>
>Sean

Absolutely, it is cheaper to buy this stuff, the other poster had something like this
for 37$ IIRC.
But the learning experience is great.
Try the scope sure, I have a frequency counter I can load in the digilab board too.
If you try the scope, then you can also make an UART in HDL, and send the trace at
highest baudrate to the PC, write some simple graphics display (I use Linux xforms
for making GUI applications), perhaps with some buttons that the PC then sends to the
FPGA board.
I dunno if you can program in C.
the frequency counter also sends the setting via RS232 (and to the LCD).

From: joseph2k on 14 Dec 2006 01:50
Jan Panteltje wrote:

> On a sunny day (10 Dec 2006 10:08:02 -0800) it happened
> sp_mclaugh(a)yahoo.com wrote in
> <1165774082.635298.65020(a)j44g2000cwa.googlegroups.com>:
>
>>Which brings me to another question... You used the TDA3560 to generate
>>your ADC sampling clock, correct? With the varicap for fine tuning. Did
>>you use any of it's other features, or just the clock? I couldn't find
>>where it outputs the chroma-locked clock (I see that it has one, but is
>>it just internal?). But it seems to be capable of doing the entire
>>demodulation process - all the way to RGB.
>
> Yes, anyways it is a PAL chip.
> You can grab the clock with any high impedance from the Xtal at pin 20.
>
>>Yes, I just realized that too! I should've ordered either 32 MHz or 64
>>MHz crystal oscillators! But I have a whole bunch of 50 MHz 8-DIPs, so
>>maybe I'll just divide one down to 25 MHz in the FPGA. Or I'll just buy
>>some more oscillators, it's not like they're expensive. I seem to be
>>getting mixed up with one of the projects you described earlier -
>>something about using a 200 MHz sampling clock. But surely that wasn't
>>with the TDA8708A, right?
>
> No, that was to generate PAL quadrature :-)
>
>>I'm a bit torn between spending $6-$10 on a VGA to DIP header (could
>>use solderless breadboard),
>
> Not sure wat you want to do here, I use a 15 pol D connector for RGB
> to the Samsung Syncmaster monitor, it has 3 BNC connectors (apart from
> the normal VGA) and I can select video input2 from the monitor front.
> Very convenient.
> I thought you were referring to the 90 degrees headers that connect to
> the digilab board.
>
>>or spending the time to solder up my own
>>solution... Same goes for the RCA header and IDC ribbons. I know I
>>could do the whole breadboard in a few hours, but being lazy, I think
>>I'm just going to pay the money. Plus my work tends to be rather messy
>>(OTOH, the picture you sent is quite clean looking).
>
> Eh, wait till yo usee the wiring on the back :-) It is done with split
> flat cable.
>
>>If I was
>>*smarter*, I'd have realized that I'm nearing the $50 range, where I
>>could just mail-order a PCB. But I'm not. :-)
>>
>>Thanks,
>>
>>Sean
>
> Absolutely, it is cheaper to buy this stuff, the other poster had
> something like this for 37$ IIRC.
> But the learning experience is great.
> Try the scope sure, I have a frequency counter I can load in the digilab
> board too. If you try the scope, then you can also make an UART in HDL,
> and send the trace at highest baudrate to the PC, write some simple
> graphics display (I use Linux xforms
> for making GUI applications), perhaps with some buttons that the PC then
> sends to the FPGA board.
> I dunno if you can program in C.
> the frequency counter also sends the setting via RS232 (and to the LCD).

This has been a rousing discussion. If i were to try to convert NTSC / PAL
analog to VGA i would lock my sampling clock to the color burst (like an
analog set) and sample the composite at 8 samples per cycle, evenly spaced.
This makes the math for the FPGA relatively simple. When you calculate the
tradeoff variables of sample rate, A/D bit depth, computational complexity
and various costs, this seems to be a sweet spot.

--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller
From: Jan Panteltje on 14 Dec 2006 07:35
On a sunny day (Thu, 14 Dec 2006 06:50:17 GMT) it happened joseph2k
<quiettechblue(a)yahoo.com> wrote in
<Ju6gh.28077$qO4.26642(a)newssvr13.news.prodigy.net>:

>This has been a rousing discussion. If i were to try to convert NTSC / PAL
>analog to VGA i would lock my sampling clock to the color burst (like an
>analog set) and sample the composite at 8 samples per cycle, evenly spaced.
>This makes the math for the FPGA relatively simple. When you calculate the
>tradeoff variables of sample rate, A/D bit depth, computational complexity
>and various costs, this seems to be a sweet spot.

Yes it makes sense to sample locked to fc.
Dutch analog TV is switched of permanently now per December 11 2006....
I have ordered a DVB-T settop box (USB) that is supposed to work with Linux
(I hope).
That way I will be able to record digitally, just like I already do with DVB-S
(satellite).
Spent a wopping 29 Euro on that thing, postage is almost as high.
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