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From: rickman on 1 Mar 2010 18:36
On Mar 1, 5:38 am, "Nial Stewart"
<nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> > I really have to say that paying for Hyperlynx once is a lot cheaper
> > than fixing board, after board, with bad SI.  In fact one re-spin of
> > the pcb is about what the tool costs.
>
> Austin,
>
> Out of interest I've asked about Hyperlynx pricing.
>
> There are many different pricing options, but the perpetual licences
> for Hyperlynx are...
>
> EXT (MHz version) line (schematic I presume) and board simulation ~ GPB £16K
>
> GHz (GHz version) line and board sim ~ GBP £38K
>
> This might be what it costs to re-spin a board if you're paying a large
> CEM to kit and build 20 Virtex boards, but for most of us a re-spin
> won't cost anything like that.
>
> We don't all work for large corporations.
>
> Nial.

Even so, I have *never* had to respin a board because of SI issues. A
full blown simulation tool is not the only way to analyze this sort of
stuff, regardless of what you will hear. Heck how often do you even
have the full details of your loading to use with a high end tool?
You have to extract that data from the layout program and they don't
pull if from a universal Gerber file. You have to be using a
compatible layout program... more big bucks, otherwise needlessly
spent.

Rick
From: Nial Stewart on 2 Mar 2010 04:54
> Even so, I have *never* had to respin a board because of SI issues.

Neither have I, but I haven't exactly been pushing the boundaries for
the last couple of years.

> A

> full blown simulation tool is not the only way to analyze this sort of

> stuff, regardless of what you will hear. Heck how often do you even
> have the full details of your loading to use with a high end tool?
> You have to extract that data from the layout program and they don't
> pull if from a universal Gerber file.


I think Hyperlynx will pull in Gerbers OK.

At least it should for what it costs.


Nial


From: Kim Enkovaara on 2 Mar 2010 05:21
rickman wrote:
> On Mar 1, 5:38 am, "Nial Stewart"

> Even so, I have *never* had to respin a board because of SI issues. A
> full blown simulation tool is not the only way to analyze this sort of
> stuff, regardless of what you will hear. Heck how often do you even
> have the full details of your loading to use with a high end tool?

I haven't seen a complex board without need for respin and SI is one
of the reasons quite often. For me complex board is 15+ layers, high
speed busses (600+MHz DDR), differential gigabit traces, board full of
components and quite big boards. Even with simulation there are
suprises, but the more time is spent on simulation the better quality
the board usually is.

Especially crosstalk is a real problem in complex boards, and without
automatic batch simulation quite impossible to handle without very
conservative design rules. And with too conservative rules the designs
do not to fit to the boards.

It quite normal in complex boards to have ibis models for most of
the chips already in the component database, and some defaults for
others and layout is extracted from the design databases. In the
more expensive tools the flow has been automated in recent years.

Next stage is power integrity simulation of the boards. With hundreds
of amps of current the power distribution is a real problem and
hard to analyze.

--Kim
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