Frustration with Vendors!
in [FPGA]
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From: rickman on 26 Feb 2010 01:43 Sometimes vendors act like they don't want you to use their parts. I am looking for rise/fall time information on an FPGA output in one voltage mode LVCMOS33 and the various drive and slew rate options. This doesn't sound like a difficult thing to ask for, but it seems to be a very difficult thing to get. I recall the rise/fall times to be something that is very common in data sheets. They just pick a set of conditions and give the data. Even if that does not match your circuit design perfectly, it is a data point to start with. In my case, I am seeing a ridiculously slow rise time with the current setting which happens to be the lowest current and slowest slew rate. I guess that is not unexpected. In fact, I'm a bit surprised we didn't see a problem with it before now. If I go with the highest drive and fast slew rate, I get very significant overshoot which is also not surprising. So obviously I need to find a happy medium. I could make up some boards with different drive settings and see how they work, but there are 10 combinations total and this is a bit of a PITA and has to involve my customer to make the measurements. Since they don't include rise time info in the data sheet, I thought, maybe I'll contact support and get the info. That was last Friday when I called thinking this was such a simple request that maybe they could answer the question on the phone... silly me. I have not received a reply from that contact yet! Yesterday I got tired of waiting and in addition to pinging support by email, I made a post in their forum. That seems to have gotten a response but not an answer. I am repeatedly told that the info would do me no good since it would not match my circuit; I can get this info from an IBIS simulation and several other ideas of how to get the info... meanwhile I'm not actually getting the info from support. I don't have a way to simulate IBIS models. I tried to convert the IBIS file to a spice model, but the resulting file was not compatible with the spice I use. I was told to manually read the IBIS model, but it is a huge thing that includes all of the IO modes with such cryptic names that I have no way of knowing which section is for which IO setting. They even have been giving me advice on how to properly design a transmission line! The guy has all but written a book of advice for me on all this, but none of the solutions work for me. It just seems absurd that support is going to so much trouble to give me advice I don't want in lieu of some very simple data I do want. So I am going to have to build a bit file with each of the various setting combinations and spend the afternoon measuring each one. It just seems like such a waste of time, but it will be easier than trying to pass the camel of support through the eye of the needle of my question. Rick
From: Uwe Bonnes on 26 Feb 2010 04:52 rickman <gnuarm(a)gmail.com> wrote: > Sometimes vendors act like they don't want you to use their parts. I > am looking for rise/fall time information on an FPGA output in one > voltage mode LVCMOS33 and the various drive and slew rate options. > This doesn't sound like a difficult thing to ask for, but it seems to > be a very difficult thing to get. I recall the rise/fall times to be > something that is very common in data sheets. They just pick a set of > conditions and give the data. Even if that does not match your > circuit design perfectly, it is a data point to start with. > In my case, I am seeing a ridiculously slow rise time with the current > setting which happens to be the lowest current and slowest slew rate. > I guess that is not unexpected. In fact, I'm a bit surprised we > didn't see a problem with it before now. If I go with the highest > drive and fast slew rate, I get very significant overshoot which is > also not surprising. Go back to the basic, starting without transmission line effects. With 10 mA source current and 10 pf load, dU/dt = 10 mA/10pF = 1V/nS 10 pF is probably no bad guestimate for one output with one pin load and some trace... So probably series termination is another approach you should consider. Bye -- Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: rickman on 26 Feb 2010 05:39 On Feb 26, 4:52 am, Uwe Bonnes <b...(a)elektron.ikp.physik.tu- darmstadt.de> wrote: > rickman <gnu...(a)gmail.com> wrote: > > Sometimes vendors act like they don't want you to use their parts. I > > am looking for rise/fall time information on an FPGA output in one > > voltage mode LVCMOS33 and the various drive and slew rate options. > > This doesn't sound like a difficult thing to ask for, but it seems to > > be a very difficult thing to get. I recall the rise/fall times to be > > something that is very common in data sheets. They just pick a set of > > conditions and give the data. Even if that does not match your > > circuit design perfectly, it is a data point to start with. > > In my case, I am seeing a ridiculously slow rise time with the current > > setting which happens to be the lowest current and slowest slew rate. > > I guess that is not unexpected. In fact, I'm a bit surprised we > > didn't see a problem with it before now. If I go with the highest > > drive and fast slew rate, I get very significant overshoot which is > > also not surprising. > > Go back to the basic, starting without transmission line effects. > With 10 mA source current and 10 pf load, dU/dt = 10 mA/10pF = 1V/nS > > 10 pF is probably no bad guestimate for one output with one pin load and > some trace... > > So probably series termination is another approach you should consider. Where did you get any of the data you are talking about? How did you come up with 10 mA? I could have done all sorts of things if I want to make assumptions, but they would be just that, assumptions and not information. The settings include current drive of 4, 8, 12, 16 and 20 mA along with speed settings of FAST and SLOW. Clearly you can't just do a calculation based on the rated current since that would leave no room for the FAST/SLOW setting. I believe I was told by one of the FPGA vendors that their parts had current controlled internal nodes which could set the slew rate. So it may be that the speed setting alone controls the slew rate of a bare pin. Like I said, that would be a good start, but until I can get an informative reply I am left only with building 10 different bit files, loading up 10 different boards and taking 10 measurements. Not my idea of a fun afternoon. Rick
From: Nial Stewart on 26 Feb 2010 06:30 > The > settings include current drive of 4, 8, 12, 16 and 20 mA along with > speed settings of FAST and SLOW. Clearly you can't just do a > calculation based on the rated current since that would leave no room > for the FAST/SLOW setting. I might be wrong, but I _think_ that in Quartus a FAST or SLOW assignment overrides the current setting, so that's fewer variations to worry about. > I am left only > with building 10 different bit files, loading up 10 different boards > and taking 10 measurements. Not my idea of a fun afternoon. Sure it wouldn't take too long to knock up a mickey mouse design that just toggles a single pin then vary the assignments. You could have a new test re-built and programmed in a minute or two. Or are there other constraints? Nial.
From: Symon on 26 Feb 2010 07:43
If I was gonna guess how FPGA's outputs with programmable drive and slew work, I'd say there are a bunch of FETs in parallel, turning on more of them for more drive. So, for 2mA, just one FET gets turned on, for 24mA, all of them do. The gate current to these FETs can be limited, which gives slower skew, or not limited which means they go as fast as possible. It would be impossible for a vendor to publish a 'rise time' for these devices, because of the many different settings, which is why the IBIS files are great. Cheers, Syms. |