Frustration with Vendors!
in [FPGA]
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From: Symon on 27 Feb 2010 15:53 On 2/26/2010 9:31 PM, austin wrote: > > Been a long time since I posted something like this... with Peter > Alfke retired from Xilinx, I wear a "white hat" all the time now, and > I am nothing but nice, and helpful (no negativity!). Who are you, and what have you done with Austin? Syms. ;-)
From: -jg on 27 Feb 2010 15:56 On Feb 28, 8:27 am, austin <aus...(a)xilinx.com> wrote: > Re: Spice > > I know that hspice has an interface to allow IBIS models to be > declared, and used, with the spice netlist. > > I suspect, "real" spice tool vendors expect one to pay for this sort > of feature, which is not part of the free UC Berkeley spice source > code (on which all the free spice versions are 'based.') So, someone > has to code the .model additions to the spice program to deal with the > IBIS data files. Unless they are doing it for fun, they probably wish > to get paid for their work: I would need some monetary motivaion now, > as coding might have been 'fun' when I was 14 years old, but that was > a long time ago. > > So, yes Hyperlynx ia not free, and neither is hspice. > > If everything used, free? I can not imagine that everyone out there > is using free schematic, free pcb layout, etc. tools! > > Someone might be, but that must be the hobby type, or student > (although students usually have free access to dozens of very powerful > tools, if they would only ask their professor!). > > Anyone with a business can certainly justify paying for something > useful, that would save them time (or money). > > I am a ham radio operator (AB6VU), and I do have my own collection of > useful free stuff, but even I have purchased some of my hobby software > when necessary (but, I will admit, I don't own any hobby software with > more than a $100 price tag). > > Austin You've somewhat missed the point. Xilinx tools are likely to be free to the vast majority of users. Xilinx PAY their employees to create models, and the tools. It's simple common sense for Xilinx to do this once, vs hundreds of users, having to either call xilinx (and so consume man-hours), or find a solution themselves. The spice models do NOT have to be full fab-mosfets ones - as you have mentioned, the device/temperature/voltage variations already swamp small tool variations. If someone wanted to get creative, they could do a competition for the best IBIS to Spice, with two categories ? : a) The Simplest, and most portable. b) A higher level of accuracy Sounds like a good final year project to me... -jg
From: -jg on 27 Feb 2010 16:03 On Feb 28, 2:59 am, Symon <symon_bre...(a)hotmail.com> wrote: > On 2/26/2010 10:46 PM, -jg wrote: > > > Why is there no simple Spice pathway to allow users do the 'sanity > > check' stuff themselves ? > > Because Spice models reveal more about the actual structure of the > device than the vendors are prepared to give. The IBIS table based > method keeps this proprietary information hidden. hmm.. sounds more like spin/deflection than a real reason, to me. I did find a useful IBIS resource web page here http://www.mentor.com/products/pcb-system-design/modeling-resources includes links to many free resources... (something FPGA vendors could learn from.. ?) -jg
From: John_H on 27 Feb 2010 16:05 On Feb 27, 3:56 pm, -jg <jim.granvi...(a)gmail.com> wrote: <snip> > If someone wanted to get creative, they could do a competition for the > best IBIS to Spice, with two categories ? : > a) The Simplest, and most portable. > b) A higher level of accuracy > > Sounds like a good final year project to me... > > -jg Or the simplest IBIS simulator with single source, single destination, simple transmission line. Kind of like what Hyperlinx was back when you could get a free version.
From: rickman on 27 Feb 2010 21:27
On Feb 27, 8:59 am, Symon <symon_bre...(a)hotmail.com> wrote: > On 2/26/2010 10:46 PM, -jg wrote: > > > Why is there no simple Spice pathway to allow users do the 'sanity > > check' stuff themselves ? > > Because Spice models reveal more about the actual structure of the > device than the vendors are prepared to give. The IBIS table based > method keeps this proprietary information hidden. > > Syms. That is not fully accurate, even if it is many vendors' party line. Yes, if they create the spice model by describing their actual circuit in the spice model, it can be reverse engineered. But just like they generated an IBIS file which only describes the behavior of the IO port, they can describe the same behavior in a spice model. In fact, I found one program from Intusoft that will convert an IBIS file into a spice model. But it has two problems. One is that it generates only one version of spice code that is not compatible with the spice program that I use. The other is that it does not work with all versions of IBIS (including the newest one) so that it won't convert all IBIS files. Those are both pretty big limitations, but it shows that a spice model can be created that does not give away proprietary information. The vendors simply feel that their customers don't "need" spice models. That goes back to exactly "who" their customers (or main customers) really are. The FPGA vendors cater to the comms markets who buy a lot of FPGAs and also buy the really high end, super expensive FPGAs. Those guys pretty much don't mind spending $5k on a tool that gets used a handful of times per year. We smaller customers, who don't have the cash to spend on a tool that merely reduces the vendor's inconvenience, prefer using open source tools that are very well supported, like LTspice, over commercial tools that are expensive and often poorly supported. Rick |