Hysteresis on dsPIC ports?
in [Design]
|
From: Joerg on 25 Jan 2010 13:57 Hello, This really blows my mind and I think I've arrived at the decision not to use their uC in the future. But a client does. It's a dsPIC and while the datasheet says that the IO ports have Schmitt characteristics there is no mention of how much hysteresis. So, I dutifully opened a support ticket asking for the hysteresis. The answer came promptly but floored me. They do not know (!). Sounds like a textbook answer from Outsourcia. I shall contact the sales office and if our app is deemed "worthy" they might or might not process such request. <shaking head> Anyhow, does anyone know what the hysteresis on dsPIC ports is? -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
From: speff on 25 Jan 2010 20:38 On Jan 25, 1:57 pm, Joerg <inva...(a)invalid.invalid> wrote: > Hello, > > This really blows my mind and I think I've arrived at the decision not > to use their uC in the future. But a client does. It's a dsPIC and while > the datasheet says that the IO ports have Schmitt characteristics there > is no mention of how much hysteresis. So, I dutifully opened a support > ticket asking for the hysteresis. The answer came promptly but floored > me. They do not know (!). Sounds like a textbook answer from Outsourcia. > I shall contact the sales office and if our app is deemed "worthy" they > might or might not process such request. > > <shaking head> > > Anyhow, does anyone know what the hysteresis on dsPIC ports is? > > -- > Regards, Joerg > > http://www.analogconsultants.com/ > > "gmail" domain blocked because of excessive spam. > Use another domain or send PM. Obviously somewhere between zero and 0.6*Vdd. ;-) They've historically maintained a minimum of 0.15*Vdd on the earlier 16C chips. So likely typical is somewhere well in between (0.3*Vdd?). Really, there are no guarantees, since it's not in the datasheet, and your best bet is to measure a few if you want a good idea of the current typical. Or use the comparator if it's important that it be close to some specific value. CMOS ST chips are almost as bad- hysteresis has a huge range before it hits the data sheet limits. Best regards, Spehro
From: Robert Baer on 26 Jan 2010 04:46 Joerg wrote: > Hello, > > This really blows my mind and I think I've arrived at the decision not > to use their uC in the future. But a client does. It's a dsPIC and while > the datasheet says that the IO ports have Schmitt characteristics there > is no mention of how much hysteresis. So, I dutifully opened a support > ticket asking for the hysteresis. The answer came promptly but floored > me. They do not know (!). Sounds like a textbook answer from Outsourcia. > I shall contact the sales office and if our app is deemed "worthy" they > might or might not process such request. > > <shaking head> > > Anyhow, does anyone know what the hysteresis on dsPIC ports is? > Measure it! Then publish and take *all* of the credit.
From: osr on 26 Jan 2010 09:26 Hand a board a copy of the email results to Dave the EE blog guy, Sit back and watch the fireworks. Steve
From: Joerg on 26 Jan 2010 11:56
osr(a)uakron.edu wrote: > Hand a board a copy of the email results to Dave the EE blog guy, Sit > back and watch the fireworks. > Oh yeah, he'd tear them apart in mid-air :-) "Sir, why are this quarter's results so dismal?" ... "Well, we have been daved." -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |