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From: maxascent on 12 Jun 2010 04:44
Just because synthesis passes your timing constraint it doesnt mean it will
pass after p&r. For instance there could be two pieces of logic at opposite
sides of the fpga connected by a long delay. So you need to look at the
static timing report to see what paths are failing. Just randomly changing
things until it works isnt the way to go.

Jon

>I've specified the constraint on the clock to the FPGA. That clock goes
to
>a DCM and Xilinx generates a constraint for the output clock of the DCM.
>
>Synthesis runs fine, I get around a 3 ns cycle time.
>
>I don't get an error about failing timing constraints until after place
and
>route has completed. I guess I just need to experiment to find out what
>works.


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