Modelsim PE vs. Aldec Active-HDL (PE)
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From: rickman on 8 Mar 2010 18:38 On Mar 8, 4:40 pm, Andy Peters <goo...(a)latke.net> wrote: > On Mar 8, 1:32 pm, rickman <gnu...(a)gmail.com> wrote: > > > On Mar 8, 6:53 am, Martin Thompson <martin.j.thomp...(a)trw.com> wrote: > > > > rickman <gnu...(a)gmail.com> writes: > > > > I find the GUI will save me a lot of typing when instantiating > > > > modules. I use the "generate test bench" feature to build a file > > > > with the meat and potatoes in it and I copy that to the higher level > > > > module. > > > > Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed > > > it :) > > > Are you saying that Emacs understands VHDL well enough to build a test > > bench for you? > > It will create a skeleton for you. > > > Will it also build a component declaration or > > instantiation automatically? These three things could be automated, > > but I have never taken the time to do it. Making it part of the > > editor makes perfect sense. > > The skeleton has a nice header, an instance of the DUT, signal > declarations for all DUT I/O and a simple clock generator. Of course > you have to create your own stimulus and add instantiations of other > models as necessary. Ok, that's what I get from the Aldec or Lattice ispLever tools. I'll have to look at EMACs sometime soon. Can it be used to do pretty print formatting on VHDL files? Rick
From: Petter Gustad on 9 Mar 2010 03:17 rickman <gnuarm(a)gmail.com> writes: > Ok, that's what I get from the Aldec or Lattice ispLever tools. I'll > have to look at EMACs sometime soon. Can it be used to do pretty > print formatting on VHDL files? Yes, it will "beautify", either the entire buffer or the current region (using C-c C-b or C-c M-b). I'm also using Emacs/Gnus writing this message and reading this newsgroup. I'm using Emacs/Mew for writing E-mail, also writing Verilog, Common Lisp, Python, C, Java, LaTex, etc., as well as doing GIT commits, diffs, creating branches, merges, even surfing the web using w3m. Dired in Emacs provides a great file browser where I can to bulk editing etc. Whenever I want to perform tedious repetitive editing tasks I will usually make a small Emacs Lisp function to do it for me... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
From: Martin Thompson on 9 Mar 2010 05:06 rickman <gnuarm(a)gmail.com> writes: > On Mar 8, 6:53�am, Martin Thompson <martin.j.thomp...(a)trw.com> wrote: >> rickman <gnu...(a)gmail.com> writes: >> > I find the GUI will save me a lot of typing when instantiating >> > modules. �I use the "generate test bench" feature to build a file >> > with the meat and potatoes in it and I copy that to the higher level >> > module. >> >> Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed >> it :) > > Are you saying that Emacs understands VHDL well enough to build a test > bench for you? Will it also build a component declaration or > instantiation automatically? These three things could be automated, > but I have never taken the time to do it. Making it part of the > editor makes perfect sense. Here's an example: Given this (for which I typed very few letters due to autocompletion and other magic): entity example is generic ( blah : integer := 5); port ( clk : in std_logic; reset : in std_logic; a : in integer; b : out integer); end entity example; I can "copy-port" and "paste as testbench" to get this (I have done nothing further to it at all): < being vhdl paste > library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------------------------------------------------------------------------------------- entity tb_example is end entity tb_example; ---------------------------------------------------------------------------------------------------------------------------------- architecture test of tb_example is -- component generics constant blah : integer := 5; -- component ports signal clk : std_logic; signal reset : std_logic; signal a : integer; signal b : integer; -- clock signal Clk : std_logic := '1'; -- finished? signal finished : std_logic; begin -- architecture test -- component instantiation DUT: entity work.example generic map ( blah => blah) port map ( clk => clk, reset => reset, a => a, b => b); -- clock generation Clk <= not Clk after 10 ns when finished /= '1' else '0'; -- waveform generation WaveGen_Proc: process begin finished <= '0'; -- insert signal assignments here finished <= '1'; report (time'image(now) & " Finished"); wait; end process WaveGen_Proc; end architecture test; ---------------------------------------------------------------------------------------------------------------------------------- configuration tb_example_test_cfg of tb_example is for test end for; end tb_example_test_cfg; ---------------------------------------------------------------------------------------------------------------------------------- < end vhdl paste > I still need to update the vhdl-mode config so that clk doesn't get defined twice - I broke that at some point, and haven't gone back to fix it properly, I just delete the line. That feels very lazy, now I'm admitting it :) Cheers, Martin -- martin.j.thompson(a)trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
From: Nial Stewart on 9 Mar 2010 06:37 > Are you saying that Emacs understands VHDL well enough to build a test > bench for you? Will it also build a component declaration or > instantiation automatically? These three things could be automated, > but I have never taken the time to do it. Making it part of the > editor makes perfect sense. The problem with emacs is you need three knuckles in each finger to drive it. The following perl script builds a basic testbench from a *.vhd entity. http://www.nialstewartdevelopments.co.uk/download/tb_gen.pl It's not perfect (generics throw it I think, I keep meaning to fix that) but it's saved me a lot of time. Nial.
From: Andy Peters on 9 Mar 2010 13:54
On Mar 9, 4:37 am, "Nial Stewart" <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote: > > Are you saying that Emacs understands VHDL well enough to build a test > > bench for you? Will it also build a component declaration or > > instantiation automatically? These three things could be automated, > > but I have never taken the time to do it. Making it part of the > > editor makes perfect sense. > > The problem with emacs is you need three knuckles in each finger to > drive it. Remap the caps-lock key to CTRL and you're back to only two knuckles :) -a |