Xilinx and Multi-port memories
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From: Rob Doyle on 25 Dec 2009 23:38 I'm trying to build a register-file for an ALU which has 3 read ports and 1 write port. There is a single clock design but I need to assume that all ports are in use on every clock cycle, worst case. I can envision implementing this using 3 Dual Port Memories each with one read port and one write port as follows: Sorry - ASCII ART (use fixed width font) Address lines elided - +-------+ +--->| RAM1 | -----> read1 | +-------+ | +-------+ write1 --+--->| RAM2 | -----> read2 | +-------+ | +-------+ +--->| RAM3 | -----> read3 +-------+ Is this the best way to do this? If I *had* to add another write port to the memory - can you do that using memories? I can't see it... Thanks in advance. Rob Doyle
From: whygee on 26 Dec 2009 02:15 Rob Doyle wrote: > Is this the best way to do this? AFAIK, IMHO, etc. yes > If I *had* to add another write port to the memory - can you do that > using memories? I can't see it... Good question indeed. There are some ways to fake a dual-write register set using single-write blocks but nothing I know can really do it. If you are designing a CPU, this can badly affect the ISA and/or performance. That's why "most RISC CPU" only have 2R1W instruction. One simple way to double the number of ports is by clocking the register set 2x faster, but I assume from your post that it's what you intend to do. That's a good bet if your pipeline/clock/timing can handle it, the memory blocks can often run faster than the logic on some FPGAs. Another method is to implement a register/buffer/write cache that gets written back to the main register set on the following cycle. The method assumes that the 2W instructions are not very common and it stalls the pipeline for one cycle in order to perform the write back, in case the following instruction does a write too. A special path must also forward the recently written value and bypass the read ports. Yet another method splits the register set into two parts, say the odd and even banks. The ISA will specify that the 2W instructions can not write to two registers of the same bank. The restriction can be loosened a bit with more banks (4 or 8) depending on the available resources. As far as I know, the venerable Alpha EV6 used powerful combinations of these methods, implementing the 32-register set with 2 huge banks that could handle 4 simultaneous instructions at once (with the help of register renaming and out-of-order execution). comp.arch readers will fill the gaps :-) > Thanks in advance. keep us informed of your advances, > Rob Doyle yg -- http://ygdes.com / http://yasep.org
From: Muzaffer Kal on 26 Dec 2009 15:14 On Fri, 25 Dec 2009 21:38:48 -0700, Rob Doyle <radioengr(a)gmail.com> wrote: > >If I *had* to add another write port to the memory - can you do that >using memories? I can't see it... One thing you can do is to have two copies of your register file and keep a 'most-recently-written' state for each location. Then each read path has an additional 2-1 mux after it controlled by the same signal (and a comparator for the read address). This should give the datapath you want but whether the extra delay is acceptable depends on your requirements. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
From: Amal on 28 Dec 2009 01:17 On Dec 26, 3:14 pm, Muzaffer Kal <k...(a)dspia.com> wrote: > On Fri, 25 Dec 2009 21:38:48 -0700, Rob Doyle <radioe...(a)gmail.com> > wrote: > > > > >If I *had* to add another write port to the memory - can you do that > >using memories? I can't see it... > > One thing you can do is to have two copies of your register file and > keep a 'most-recently-written' state for each location. Then each read > path has an additional 2-1 mux after it controlled by the same signal > (and a comparator for the read address). This should give the datapath > you want but whether the extra delay is acceptable depends on your > requirements. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Xilinx supports 3-port memories as well if it helps. You can have one read/write port and two read ports with 3 different addresses. You can either infer it or instantiate the component directly. Cheers, -- Amal
From: whygee on 28 Dec 2009 03:40
hello, Amal wrote: > Xilinx supports 3-port memories as well if it helps. You can have one > read/write port and two read ports with 3 different addresses. > You can either infer it or instantiate the component directly. the OP and the thread are speaking about multiple write port, because multiple read ports are trivially implemented. However, simultaneously having 2 read AND 2 write ports (4 simultaneous addresses, for example) is not as easy and I guess that few synthesisers will infer the correct SRAM blocks. > Cheers, > -- Amal happy new year, yg -- http://ygdes.com / http://yasep.org |