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From: Symon on 28 Mar 2010 15:38
On 3/26/2010 9:13 PM, radarman wrote:
>
> I've only done one other "high speed" design, with a Gig-E PHY, but I
> was able to get all of the signals to within +/- 5 mils on that board.

When you did this, you took into account the different flight times in
the packages themselves, I hope! For sure the leadframes don't have
matched lengths on the signals from the die to the PCB pad.

In summary, what the other guys said, 6 inches a ns!

Cheers, Syms.
From: John_H on 28 Mar 2010 17:27
On Mar 28, 1:22 pm, KJ <kkjenni...(a)sbcglobal.net> wrote:
>
> If you're going to feed the clock back, then you'll want to parallel
> terminate to ground rather than series terminate at the source.

I figured the external lines are small enough that the transmission
line characteristics are no longer as important as the lumped model.
Having a series resistor could help the transmitter avoid too much of
a surge. The termination at the final destination is the classical
version, however. Having room for both can help, perhaps more than
hinder.
From: John_H on 28 Mar 2010 17:28
On Mar 28, 3:38 pm, Symon <symon_bre...(a)hotmail.com> wrote:
> On 3/26/2010 9:13 PM, radarman wrote:
>
>
>
> > I've only done one other "high speed" design, with a Gig-E PHY, but I
> > was able to get all of the signals to within +/- 5 mils on that board.
>
> When you did this, you took into account the different flight times in
> the packages themselves, I hope! For sure the leadframes don't have
> matched lengths on the signals from the die to the PCB pad.
>
> In summary, what the other guys said, 6 inches a ns!
>
> Cheers, Syms.

The flight times in the package shouldn't hit the timing budget at
all. The timing for both the SRAM and FPGA will be worst case for any
pin. And what's a few 10s of picoseconds?
From: Symon on 28 Mar 2010 17:42
On 3/28/2010 10:28 PM, John_H wrote:
> On Mar 28, 3:38 pm, Symon<symon_bre...(a)hotmail.com> wrote:
>> On 3/26/2010 9:13 PM, radarman wrote:
>>
>>
>>
>>> I've only done one other "high speed" design, with a Gig-E PHY, but I
>>> was able to get all of the signals to within +/- 5 mils on that board.
>>
>> When you did this, you took into account the different flight times in
>> the packages themselves, I hope! For sure the leadframes don't have
>> matched lengths on the signals from the die to the PCB pad.
>>
>> In summary, what the other guys said, 6 inches a ns!
>>
>> Cheers, Syms.
>
> The flight times in the package shouldn't hit the timing budget at
> all. The timing for both the SRAM and FPGA will be worst case for any
> pin. And what's a few 10s of picoseconds?

Well, I agree, but did you read his post? He's making trace lengths
match to within 5 mils! That's what I'm trying to suggest may be a waste
of effort.

Cheers, Syms.

p.s. FWIW, you can get the flight times of BGA packages from Xilinx, if
you ask nicely.
From: John_H on 29 Mar 2010 00:03
On Mar 28, 5:42 pm, Symon <symon_bre...(a)hotmail.com> wrote:
>
> Well, I agree, but did you read his post? He's making trace lengths
> match to within 5 mils! That's what I'm trying to suggest may be a waste
> of effort.

I missed that. My recollection was the lengths were varied between
250 and 750 mils and he hadn't changed that decision yet. I need to
pay more attention, I guess.

TIMING BUDGET !!!!

I had an engineer at my previous place of employ who quite literally
"broke" a layout person with the outrageous constraints for the DDR2,
mostly waaaay too tight and sometimes conflicting.

Do the budget, know the needs, plan the clock, open your windows.
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