Picking N-th ready element (e.g. in an OOO scheduler)
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From: jacko on 15 Jul 2010 13:59 With the superstall, pick second or swapped third. No lower indexing is used.
From: jacko on 15 Jul 2010 14:31 If you run a double wire from each of the drains to the driven node, the rail short becomes a rail long with fast cmos, and it becomes slighly more capacitive... but does allow the switch on time V(GS) to reduce rail short, and turn off power loss in general. The turn on power is less, as the drain load is smaller, so all current goes to the driven gate. The extra tiny delayed current to the switching off driver may be lowered by placing a diode in each of the wires just before the driven gate. This would isolate the return wire more (the switching off one), Maybe useful => Placing the channel opposite the conductiong channel diven with an opposing phase, but with a V(GS)on exceeding the max volt of the chip (never conducts but accumulates charge) the secondary channel charge may inject or suck for faster switch on. Use a higher doping for the antiphase channel. ref DISCO-FET.
From: MitchAlsup on 15 Jul 2010 15:43 On Jul 15, 1:31 pm, jacko <jackokr...(a)gmail.com> wrote: Its pretty clear, from your description, you have no idea as to how to do the circuit design or physical layout of such a picker. Like a fast adder, it requires a careful choice of gates, and then careful sizing of those gates to achieve best resolution delay. There is no reason in deep submicron to resort to any dynamic logic structures, espectially in moderate sized pickers. So in the intrest of fair play, I have enclosed a link to the schematic of my 1:32 picker. Why don't you do the same? http://img692.imageshack.us/img692/4593/comparch.jpg Mitch
From: jacko on 15 Jul 2010 17:24 On Jul 15, 8:43 pm, MitchAlsup <MitchAl...(a)aol.com> wrote: > On Jul 15, 1:31 pm, jacko <jackokr...(a)gmail.com> wrote: > > Its pretty clear, from your description, you have no idea as to how to > do the circuit design or physical layout of such a picker. > Like a fast adder, it requires a careful choice of gates, and then > careful sizing of those gates to achieve best resolution delay. > There is no reason in deep submicron to resort to any dynamic logic > structures, espectially in moderate sized pickers. Yes, tis true your gate library has no low power double wire interconnects. > So in the intrest of fair play, I have enclosed a link to the > schematic of my 1:32 picker. Why don't you do the same? > > http://img692.imageshack.us/img692/4593/comparch.jpg > > Mitch
From: jacko on 15 Jul 2010 17:50
> So in the intrest of fair play, I have enclosed a link to the > schematic of my 1:32 picker. Why don't you do the same? > > http://img692.imageshack.us/img692/4593/comparch.jpg > > Mitch A ready to picked mux, I suppose that would be connected to an invalidate/empty/refill flip-flop/signal (x32) and a 32 to 1 way mux to get the picked. I'd say using common OR rail, or maybe AND rail with negative logic. It would also be a common module for say a retire instruction 1 of 32. A 32 way priority selector. In effect quite a compact shuffle queue component. ok. So picking N would be a matter of assigning to a seperate queue based on target register in the speculative/or regular register pool. To prevent queue imbalances. Just wonder if the register read muxes could be rotated so that each queue could access a percentage too. |