Prev: Cheap Wholesale Air Force One 25 Women
Next: x86 simulator (Was Re: RISC load-store verses x86 Add from memory.)
From: Andy Glew "newsgroup at on 17 Jul 2010 20:35
On 7/17/2010 3:51 PM, MitchAlsup wrote:
> On Jul 17, 11:19 am, Andy Glew<"newsgroup at comp-arch.net"> wrote:
>> Plus your response to Mitch:
>> Dual gate FETs with differential doping and antiphase. (I've thought
>> about such stuff: if you could make a dual gate that was well aligned
>> and matched, you could have an XOR that is cheaper than a NAND gate.
>> But the experts always tell me that, while in theory it might work, in
>> practice with variations and tolerances it has no chance.)
>
> AMD has a patent on such an XOR gate using two raised FIN FET
> diffusion channels, one side doped N the other doped P. I suspect
> ohers have similar patents on different transistor technologies that
> amount ot the same things.
> But the technology discussion taking place herein, requires nothing
> outside of pure CMOS and for the most part pure logic-gates.


Patent number, Mitch? Is it yours? (I'm lazy, but I'll go search if
you make me.)
From: jacko on 17 Jul 2010 21:33
On 17 July, 23:40, Andy Glew <"newsgroup at comp-arch.net"> wrote:
> On 7/17/2010 10:03 AM, jacko wrote:
>
> > No dependence on DFET. The dual wire thing is not dependent on it
> > either. The dual wires just make the metal routing between the drains
> > longer and so with higher resistance. Any metal T node works like a
> > potential divider. It's just to take advantage of any parasitic
> > resistance, or stripline characteristic impedence (at high speed and
> > the longer route) versus resistance.
>
> > So back to pickers as that is a process (metal layer) factor, not a
> > logical gate factor..
>
> You've just said several things that are red flags in modern VLSI.
>
> "Potential divider".  => power wasting, unreliable in the presence of
> variation.

A resistive metal wire metal layer called a node or routed wire or a
connection using metal is a resistor. A small one yes but the one
between the drains needs to be bigger. The one between gate output and
next gate input benefits from not being shunted by the turning off
device in the driver. I called it a potential divider, not a power
wasting potential divider.

T vs. U. Top left and top right of the character are the two drains of
the driver. Bottom centre is the driven gate pair attatchment point.
QED.

T resistance is ((X/2)+FET)/2+Y
U resistance is (Y+FET+(X/2))/2 for a simplistic understanding of the
two wires of length Y between gates.
X is within the gate cell (T) or before the driven gate (U). Y is
routed inter-gate wire (T) or wires (U)
T X resistance is the switching short
U (2Y+X) resistance is the switching short => power save
T [((X/2)+FET)//(Y+Cin)]+(X/2) is drive shunt with // being parallel
U ((Y+FET+(X/2))//Cin)+Y+(X/2) is drive shunt
If volts at Cin is opposite of applied drive ... charge current??

Simplist idea is route two wires between gates as supplied in the
library, then cut the join beteen them at the driving output end,
while still maintaing a connection to each wire at that end with at
least one FET.

> "process (metal layer) factor, not a logical gate factor".  => the whole
> trend of the last decade in VLSI design has been to wind ourselves back
> to just thinking in terms of logical gates, to avoid nearly all of the
> neat tricks dependent on particular process characteristics.
>
> > I would avoid multiple picking from the same queue.
>
> And now you have missed the whole point of the discussion.
>
> Or, rather, you are talking about a different scheduler design -
> myltiple 1 pickers, rather than 1 picker picking N ready elements of
> priority 1..N.

Yes N * (1-pickers)

> Your ideas may be good, but it is immensely frustrating to go around and
> around like this.  If you want to change to a different topic, say so.

From: jacko on 17 Jul 2010 21:38
On 18 July, 01:35, Andy Glew <"newsgroup at comp-arch.net"> wrote:
> On 7/17/2010 3:51 PM, MitchAlsup wrote:
>
> > On Jul 17, 11:19 am, Andy Glew<"newsgroup at comp-arch.net">  wrote:
> >> Plus your response to Mitch:
> >> Dual gate FETs with differential doping and antiphase.  (I've thought
> >> about such stuff:  if you could make a dual gate that was well aligned
> >> and matched, you could have an XOR that is cheaper than a NAND gate.
> >> But the experts always tell me that, while in theory it might work, in
> >> practice with variations and tolerances it has no chance.)
>
> > AMD has a patent on such an XOR gate using two raised FIN FET
> > diffusion channels, one side doped N the other doped P. I suspect
> > ohers have similar patents on different transistor technologies that
> > amount ot the same things.
> > But the technology discussion taking place herein, requires nothing
> > outside of pure CMOS and for the most part pure logic-gates.
>
> Patent number, Mitch?  Is it yours?  (I'm lazy, but I'll go search if
> you make me.)

The DISCO-FET has prior art as this group is filed as public.
The second FET not conducting I guess makes it a unique inventive step.
From: jacko on 17 Jul 2010 21:47
It never conducts, I think it's purpose is to accumulate charge
carriers and oscilllate them normal to the plane of the wafer. A
bigger gate, as it has local drive from the via from the drain just
above part of it. Higher doping gives better hole/electon injection.
From: MitchAlsup on 18 Jul 2010 17:19
On Jul 17, 8:33 pm, jacko <jackokr...(a)gmail.com> wrote:
> A resistive metal wire metal layer called

Schematics or <just stop>

As to the patent, no it is not mine, and clever enough it took me 2
hours to figure out that it really was an XOR gate. Circa 2009.

Mitch
First  |  Prev  |  Next  |  Last
Pages: 1 2 3 4 5 6 7 8 9
Prev: Cheap Wholesale Air Force One 25 Women
Next: x86 simulator (Was Re: RISC load-store verses x86 Add from memory.)