Picking N-th ready element (e.g. in an OOO scheduler)
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From: jacko on 15 Jul 2010 17:55 I do wonder if the registers should actually store a pointer to the pool, and insert occasional mock moves to keep the pool ringing linear, without stagnant can not refill entries.
From: Andy Glew "newsgroup at on 16 Jul 2010 23:17 On 7/15/2010 2:24 PM, jacko wrote: > On Jul 15, 8:43 pm, MitchAlsup<MitchAl...(a)aol.com> wrote: >> There is no reason in deep submicron to resort to any dynamic logic >> structures, espectially in moderate sized pickers. > > Yes, tis true your gate library has no low power double wire > interconnects. It's not so much the lack of "low power double wire interconnects" - by which I think you mean what folks in my experience call LVDS, low voltage differential signalling. It's that your description, what I can make of it, seems to be using dynamic or wired logic. And we have spent the last 5-10 years learning not to do dynamic or wired logic, because it is not reliable in deep submicron. Or you using dynamic or wired logic? A schematic would show. (My usual plaint about comp.arch needing a way to exchange diagrams, line drawings. I am working, in my not-so-copious spare time, on having diagram editing on comp-arch.net.) By the way, a minor quibble with Mitch: it's not so much that we don't have reasons to want to use dynamic structures, it's that the reasons for not using dynamic structures outweigh the reasons for using them.
From: jacko on 17 Jul 2010 09:18 On Jul 17, 4:17 am, Andy Glew <"newsgroup at comp-arch.net"> wrote: > On 7/15/2010 2:24 PM, jacko wrote: > > > On Jul 15, 8:43 pm, MitchAlsup<MitchAl...(a)aol.com> wrote: > >> There is no reason in deep submicron to resort to any dynamic logic > >> structures, espectially in moderate sized pickers. > > > Yes, tis true your gate library has no low power double wire > > interconnects. > > It's not so much the lack of "low power double wire interconnects" - by > which I think you mean what folks in my experience call LVDS, low > voltage differential signalling. > > It's that your description, what I can make of it, seems to be using > dynamic or wired logic. And we have spent the last 5-10 years learning > not to do dynamic or wired logic, because it is not reliable in deep > submicron. Take one standard inverter, disconnect drains, these two new output nodes are the pair. They route together to another say inverter, an join together at the second inverter input node. This makes the rail short current path longer and due to the input capacitance of the driven not gate's transistor gates, reduces power switch off loss in the driving not gate, and turn on power loss in the driving not gate as all current flows to the driven gate pair. That's a low power double wire interconnect. Not as ameanable to rat's nest optimization unless wire are routed in pairs, and kept in pairs. Not differential drive, as only one is driven, the other goes HiZ. Further to this design, the wire pair joining at an input node, can have a diode half bridge +-|>|-+-|>|-+ with centre being the driven node. The differential of resistances of conducting and non conducting diodes futher skews the two wire potential divider, in the power favour. The actual FETs can have two gates yes? But if in parallel these gates be with close proximity of channels see, then antiphase drive is small transit time... Pity it's always on, ... what if V(GS) was lifted for one of them? by doping of the depletion for more depletion needed? The carrier jumping would still occur F(tmax) going higher. A bit like a burried layer carrier n+ in bipolar, but active... The second gate is just driven antiphase by it's output for that miller capacitance effect??!! Is this making sense to you?
From: jacko on 17 Jul 2010 09:21 Direct Injection Switching Channel Organization (DISCO) FET
From: MitchAlsup on 17 Jul 2010 09:30
On Jul 16, 10:17 pm, Andy Glew <"newsgroup at comp-arch.net"> wrote: > By the way, a minor quibble with Mitch: it's not so much that we don't > have reasons to want to use dynamic structures, it's that the reasons > for not using dynamic structures outweigh the reasons for using them. I do not believe that I have said anything positive or negative about dynamic logic. And I did live through the vast unlearning process, much like Andy. But my point to jacko was that his use of words is so foreign to the standard dictum of logic designers, that we cannot understand what he attempts to try to say without some schematics. Apparently he has no access to draw tools and free image hoisting, or does not care to actully get his point across. His english, in the words of Dirty Harry, "Ain't making it". In particular, his double wire interconnects could be: a) True-Complement signals b) Hot Vdd and Vss signals c) CVSL logic d) LVDS logic e) or a number of other design styles. ONLY A SCHEMATIC WILL END THE CONFUSION--jacko--so go do one. Mitch |