Picking N-th ready element (e.g. in an OOO scheduler)
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From: jacko on 17 Jul 2010 09:30 http://nibz.googlecode.com/files/disco.gif To paint you a DISCO-FET or DFET picture.
From: Andy Glew "newsgroup at on 17 Jul 2010 12:19 On 7/17/2010 6:18 AM, jacko wrote: > On Jul 17, 4:17 am, Andy Glew<"newsgroup at comp-arch.net"> wrote: >> On 7/15/2010 2:24 PM, jacko wrote: >> >>> On Jul 15, 8:43 pm, MitchAlsup<MitchAl...(a)aol.com> wrote: >>>> There is no reason in deep submicron to resort to any dynamic logic >>>> structures, espectially in moderate sized pickers. >> >>> Yes, tis true your gate library has no low power double wire >>> interconnects. >> >> It's not so much the lack of "low power double wire interconnects" - by >> which I think you mean what folks in my experience call LVDS, low >> voltage differential signalling. >> >> It's that your description, what I can make of it, seems to be using >> dynamic or wired logic. And we have spent the last 5-10 years learning >> not to do dynamic or wired logic, because it is not reliable in deep >> submicron. > > Take one standard inverter, disconnect drains, these two new output > nodes are the pair. They route together to another say inverter, an > join together at the second inverter input node. This makes the rail > short current path longer and due to the input capacitance of the > driven not gate's transistor gates, reduces power switch off loss in > the driving not gate, and turn on power loss in the driving not gate > as all current flows to the driven gate pair. > > That's a low power double wire interconnect. Not as ameanable to rat's > nest optimization unless wire are routed in pairs, and kept in pairs. > Not differential drive, as only one is driven, the other goes HiZ. > > Further to this design, the wire pair joining at an input node, can > have a diode half bridge +-|>|-+-|>|-+ with centre being the driven > node. The differential of resistances of conducting and non conducting > diodes futher skews the two wire potential divider, in the power > favour. > > The actual FETs can have two gates yes? But if in parallel these gates > be with close proximity of channels see, then antiphase drive is small > transit time... Pity it's always on, ... what if V(GS) was lifted for > one of them? by doping of the depletion for more depletion needed? The > carrier jumping would still occur F(tmax) going higher. A bit like a > burried layer carrier n+ in bipolar, but active... The second gate is > just driven antiphase by it's output for that miller capacitance > effect??!! > > Is this making sense to you? Yes, but... Now I remember. You're the DISCO FET guy. Now, I think the DISCO FET sounds interesting. Interesting enough that I went and looked it up a few years (?) ago when I first noticed you posting about it. I am not competent to pass judgement on it with my current knowledge, and, to be frank, I think that it is unlikely to be worth my while to study more. I'd gladly talk with you about it over a beer or the like, but these incoherent USEnet exchanges make it sound even more suspect. Plus your response to Mitch: >http://nibz.googlecode.com/files/disco.gif > >To paint you a DISCO-FET or DFET picture. is just plain garbage. A pretty picture, an icon. The most generous hope is that you gave the wrong URL. Face it, JackO: you're a crank about the DISCO FET. Just like I'm a crank about OOO execution, lightweight threading, and capabilities. And some of my best friends are cranks about actoring large numbers, etc. Now, please don't get insulted when I say you are a crank. Cranks are my people. I'm a crank. Cranks occasionally come up with good ideas. But there are so many cranks with bad ideas that we have to try really, really, hard to communicate clearly and coherently. So that either our good ideas can be perceived, or, possibly, so that our bad ideas can be recognized. -- Warning flags in your description: Potential dividers Dual gate FETs with differential doping and antiphase. (I've thought about such stuff: if you could make a dual gate that was well aligned and matched, you could have an XOR that is cheaper than a NAND gate. But the experts always tell me that, while in theory it might work, in practice with variations and tolerances it has no chance.) Like I said above, not my area of expertise. I prefer to say "not my area of *current* expertise, although perhaps *potential*", mainly because I like bad puns, but also because I'd be willing to go and take the time to become an expert in the area, except that I don't see enough likelihood of payback to make it worthwhile. So, in the meantime, I rely on the expertise of others, such as my former co-workers at Intel. And it doesn't pass their muster. -- Now, if I may recapitulate our discussion: 1) I started with a post about picking an N-th ready element using a carry free arithmetic technique - which Mitch usefully characterizes as being something like a multiplier array. 2) Mitch has shared with us his circuits for pickers for moderate size schedulers - 32 entries or so. Mitch's circuits look good for small schedulers, while the techniques I describe might be required for really large schedulers. Perhaps too large to be of practical use. 3) You, JackO, chimed in with some of your own scheduler ideas. Unfortunately, I am not able to get a clear picture of them - they seem to involve swapping head entries, etc. I thought that it sounded like dynamic logic, but I think that you have explained that may be a misunderstanding. Mitch and I would like to understand them, which, to us, means schematics, when words fail. (Once again my usual complaint about not having drawings on comp.arch...) 4) You have just revealed or reminded us, JackO, about your DISCO FET. It appears likely that the circuits you were describing depend on the possibly magical or wonderful properties of the DISCO FET. Again, don't take the terms "magical or wonderful" pejoratively - or at least not excessively so. If the DISCO FET works, then it sounds wonderful. But that's a separate discussion. However, I am very suspicious of circuits that depend on the magical or wonderful properties of new devices. It's not that this can't happen - heck, look at all the fuss about the memristor. Or what I said above about matched dual gates making XOR really cheap. It's just that, when we are discussing new circuits that depend on "magical or wonderful" properties of new devices, it's really good to be able to delineate what we are depending on. Don't just assume that everyone knows or agrees about your new device. Say "I have a new device, it is better in the following ways, and here's a circuit that takes advantage of it." All this being said, I still don't see how the DISCO FET makes your circuit work. Let me be honest: I am not interested in words on this topic any more. Perhaps a picture. But at this point I'm not sure if any more effort is warranted.
From: Andy Glew "newsgroup at on 17 Jul 2010 12:28 On 7/17/2010 9:19 AM, Andy Glew wrote: > On 7/17/2010 6:18 AM, jacko wrote: \> 3) You, JackO, chimed in with some of your own scheduler ideas. > Unfortunately, I am not able to get a clear picture of them - they seem > to involve swapping head entries, etc. I thought that it sounded like > dynamic logic, but I think that you have explained that may be a > misunderstanding. > > Mitch and I would like to understand them, which, to us, means > schematics, when words fail. (Once again my usual complaint about not > having drawings on comp.arch...) > > 4) You have just revealed or reminded us, JackO, about your DISCO FET. > It appears likely that the circuits you were describing depend on the > possibly magical or wonderful properties of the DISCO FET. > > Again, don't take the terms "magical or wonderful" pejoratively - or at > least not excessively so. If the DISCO FET works, then it sounds > wonderful. But that's a separate discussion. > > However, I am very suspicious of circuits that depend on the magical or > wonderful properties of new devices. It's not that this can't happen - > heck, look at all the fuss about the memristor. Or what I said above > about matched dual gates making XOR really cheap. > > It's just that, when we are discussing new circuits that depend on > "magical or wonderful" properties of new devices, it's really good to be > able to delineate what we are depending on. Don't just assume that > everyone knows or agrees about your new device. Say "I have a new > device, it is better in the following ways, and here's a circuit that > takes advantage of it." > > All this being said, I still don't see how the DISCO FET makes your > circuit work. If your scheduler circuit ideas do not depend on the DISCO FET, great, that's best and easiest to understand. (Then it is just unfortunate confusion that the DISCO FET was dragged into this.) If your scheduler circuit ideas do depend on the DISCO FET, can you tell us why, what special feature of the DISCO FET makes this work, when it doesn't work with ordinary devices? And, in either case, a picture would help. Hand-drawn on a piece of paper and scanned, if nothing else.
From: jacko on 17 Jul 2010 13:03 No dependence on DFET. The dual wire thing is not dependent on it either. The dual wires just make the metal routing between the drains longer and so with higher resistance. Any metal T node works like a potential divider. It's just to take advantage of any parasitic resistance, or stripline characteristic impedence (at high speed and the longer route) versus resistance. So back to pickers as that is a process (metal layer) factor, not a logical gate factor.. I would avoid multiple picking from the same queue. Divide the queue based on target 'register'. In this way the register pool allocation algorithm can be chosen to balance the queues, and write port contention is divided by the queue splitting ratio. Avoid register writeback by inserting 'move with source invalidate' (invalidate is unnecessary as the pool gets recycled, and is 'big enough'). Avoid read port contention of the register pool by making only a certain percentage of it readable in any cycle to an instruction waiting to become ready. Alter the percent part available on a cyclic sequence. N-picking then becomes a 1-picking problem. Cheers Jacko
From: jacko on 17 Jul 2010 13:57
> Dual gate FETs with differential doping and antiphase. (I've thought > about such stuff: if you could make a dual gate that was well aligned > and matched, you could have an XOR that is cheaper than a NAND gate. > But the experts always tell me that, while in theory it might work, in > practice with variations and tolerances it has no chance.) Try a burried 2-lambda gate. |