Please help, Xilinx FIFO problem!
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From: maxascent on 21 Dec 2009 05:32 Well once you have written and tested your own fifo then you would have it for any other project. It seems like you have wasted a lot of time already trying to fix the Xilinx version so I dont see that you have anything to loose by creating your own. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Symon on 21 Dec 2009 05:56 Antti wrote: > > Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY > flags present. > > signals at input correct, as expected (checked with ChipScope) > signals at output: > - double value > - missing 1, 2 or 3 values > - FIFO will read out random number of OLD entries, this could be 4 > values, or 50% of the FIFO old values > I know you will have read this. Can you think of any reason why the Xilinx work-around wouldn't work because of your specific implementation? It seems to have different work-arounds depending on whether the read clock is faster or slower than the write clock. Do your clocks change frequency? Are you sure your clocks don't have any glitches? The reset also? Power's OK? Is your office made of Cobalt 60? HTH., Syms.
From: Antti on 21 Dec 2009 06:01 On Dec 21, 12:56 pm, Symon <symon_bre...(a)hotmail.com> wrote: > Antti wrote: > > > Xilinx Coregen FIFO, dual clock, most options disable, only FULL EMPTY > > flags present. > > > signals at input correct, as expected (checked with ChipScope) > > signals at output: > > - double value > > - missing 1, 2 or 3 values > > - FIFO will read out random number of OLD entries, this could be 4 > > values, or 50% of the FIFO old values > > I know you will have read this. > > Can you think of any reason why the Xilinx work-around wouldn't work > because of your specific implementation? It seems to have different > work-arounds depending on whether the read clock is faster or slower > than the write clock. Do your clocks change frequency? > > Are you sure your clocks don't have any glitches? The reset also? > Power's OK? Is your office made of Cobalt 60? > > HTH., Syms. 1) I entered the clock figures in FIFO16 implementationm, but the error also happens with BRAM based FIFO that do not need workarounds 2) Clocks DO NOT CHANGE ever, one is MGT recovered clock 125MHz write, one is PLB clock 62.5MHz read 3) Power OK? Well the problem happens at 2 different sites, hm yes it could be still be power problem 4) My office is not of Cobalt 60, ... and its cold here too Antti
From: Antti on 21 Dec 2009 06:04 On Dec 21, 12:32 pm, "maxascent" <maxasc...(a)yahoo.co.uk> wrote: > Well once you have written and tested your own fifo then you would have it > for any other project. It seems like you have wasted a lot of time already > trying to fix the Xilinx version so I dont see that you have anything to > loose by creating your own. > > Jon > If you REALLY need todo something else, when your time is at absolute premium And if the system working (except occasional errors about 2 of fiber packets are corrupt) Then you do not go replacing Xilinx validated FIFO solutions with your own, if there are other options. If 2 completly different FIFO implementations both have same error? you think 3rd one would instantly work? Could be, yes. Antti
From: maxascent on 21 Dec 2009 06:29
>On Dec 21, 12:32=A0pm, "maxascent" <maxasc...(a)yahoo.co.uk> wrote: >> Well once you have written and tested your own fifo then you would have i= >t >> for any other project. It seems like you have wasted a lot of time alread= >y >> trying to fix the Xilinx version so I dont see that you have anything to >> loose by creating your own. >> >> Jon =A0 =A0 =A0 =A0 >> >If you REALLY need todo something else, when your time is at absolute >premium >And if the system working (except occasional errors about 2 of fiber >packets are corrupt) >Then you do not go replacing Xilinx validated FIFO solutions with your >own, if there are other options. > >If 2 completly different FIFO implementations both have same error? >you think 3rd one would instantly work? Could be, yes. > >Antti > > In my opinion people tend to use coregen far too often. Looking through some of Xilinx code it is awfull. I went down the route of writing my own fifos not because I had a problem with Xilinx fifos but because I believe a fifo written by myself is a lot more flexible and simulates faster than the Xilinx version. I also know to as good a degree as I can test that it will work 100%. I dont really think you can say that their fifos have been validated 100% if they have to release patches for them. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com |