Please help, Xilinx FIFO problem!
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From: Antti on 21 Dec 2009 06:42 On Dec 21, 1:29 pm, "maxascent" <maxasc...(a)yahoo.co.uk> wrote: > >On Dec 21, 12:32=A0pm, "maxascent" <maxasc...(a)yahoo.co.uk> wrote: > >> Well once you have written and tested your own fifo then you would have > i= > >t > >> for any other project. It seems like you have wasted a lot of time > alread= > >y > >> trying to fix the Xilinx version so I dont see that you have anything > to > >> loose by creating your own. > > >> Jon =A0 =A0 =A0 =A0 > > >If you REALLY need todo something else, when your time is at absolute > >premium > >And if the system working (except occasional errors about 2 of fiber > >packets are corrupt) > >Then you do not go replacing Xilinx validated FIFO solutions with your > >own, if there are other options. > > >If 2 completly different FIFO implementations both have same error? > >you think 3rd one would instantly work? Could be, yes. > > >Antti > > In my opinion people tend to use coregen far too often. Looking through > some of Xilinx code it is awfull. I went down the route of writing my own > fifos not because I had a problem with Xilinx fifos but because I believe a > fifo written by myself is a lot more flexible and simulates faster than the > Xilinx version. I also know to as good a degree as I can test that it will > work 100%. > I dont really think you can say that their fifos have been validated 100% > if they have to release patches for them. > > Jon > Dear Jon, I do not feel to be in health right now to write this fifo, so here is the deal: component mgt_fifo port ( din : in std_logic_vector(8 downto 0); rd_clk : in std_logic; rd_en : in std_logic; rst : in std_logic; wr_clk : in std_logic; wr_en : in std_logic; dout : out std_logic_vector(8 downto 0); empty : out std_logic; full : out std_logic); end component; if you can write fifo that i can "drop in" and the Xilinx FIFO error is gone, then i will stand up, go to postal office and send you 1000 EUR by western union. If 1000 EUR is not enough, name your price, i will consider it. there is no price on the health of our family condition is: DROP IN, WORKS, if i need to troubleshoot, then no pay. Antti
From: Symon on 21 Dec 2009 06:47 Antti wrote: > > 1) I entered the clock figures in FIFO16 implementationm, but the > error also happens with BRAM based FIFO that do not need workarounds > 2) Clocks DO NOT CHANGE ever, one is MGT recovered clock 125MHz write, > one is PLB clock 62.5MHz read > 3) Power OK? Well the problem happens at 2 different sites, hm yes it > could be still be power problem > > 4) My office is not of Cobalt 60, ... and its cold here too > > Antti > Whoops, looks like this link didn't make it with my post, sorry. http://www.xilinx.com/support/answers/22462.htm But you've read that already of course. Does temperature make any difference to its operation? Syms.
From: maxascent on 21 Dec 2009 06:55 Antti I have an async fifo that I can give you but it is in Verilog as I dont use VHDL. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Matthieu Michon on 21 Dec 2009 07:48 Hi Antti You may want to check the sources of the async FIFOs included in the FSL IP core (inside the EDK HW IP folder).
From: maxascent on 21 Dec 2009 07:50
Also I dont want any money. It's not like I am giving you a USB 3.0 core :) Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com |