Tier Logic introduces the world's first 3D FPGA
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From: -jg on 10 Mar 2010 16:54 On Mar 11, 10:41 am, rickman <gnu...(a)gmail.com> wrote: > On Mar 10, 3:14 pm, -jg <jim.granvi...(a)gmail.com> wrote: > > > > > On Mar 11, 8:25 am, Symon <symon_bre...(a)hotmail.com> wrote: > > > > Hi Jeff, > > > I've examined all the old FPGAs I've found in my office, and they all > > > seem to have three dimensions already. Even the old ones from 1986. > > > Hehe ;) - yes, even Tabula are trying to spin 3D too... > > > Still, getting back to the site itself, it seems they > > have a Stacked-die prototype path, and the main thrust is really mask- > > asic. > > > The stacked die 'emulation devices' will come at a large price > > premium, and their config density will need to be low (given this is > > top-layer stuff). > > I'd expect a power premium too... > > Stacked die? I read the eetimes article and didn't get anything about > stacked die from Tier Logic. Did I read something wrong? I thought > they were layering TFT on top of the base die to provide the config > memory which takes it out of the base die saving real estate. Yes they are, which is why I called it stacked die. - TWO die flows, one on top of the other. Base die is made, and then they have a second die-process that is more complex than just TFT, as it included connections. [Testing questions remain?] That will also be why they needed a lot more passes at the TFT section, as that's where the 'new tech' mostly lies. > They seem to be pushing their ability to more easily move to ASIC > production, but they seem to offer something to the FPGA only user as > well. A key question here will be: if you are unlikely to need ASIC, why start with their devices ? > I'm not clear on what you are saying about this in regards to Tier Logic. It was a general comment, about where there is space for new-comers, or new-products in the market. I've often found RAM dictates the Device choice, more than the Logic. -jg
From: rickman on 10 Mar 2010 17:29 On Mar 10, 4:54 pm, -jg <jim.granvi...(a)gmail.com> wrote: > On Mar 11, 10:41 am, rickman <gnu...(a)gmail.com> wrote: > > > > > On Mar 10, 3:14 pm, -jg <jim.granvi...(a)gmail.com> wrote: > > > > On Mar 11, 8:25 am, Symon <symon_bre...(a)hotmail.com> wrote: > > > > > Hi Jeff, > > > > I've examined all the old FPGAs I've found in my office, and they all > > > > seem to have three dimensions already. Even the old ones from 1986. > > > > Hehe ;) - yes, even Tabula are trying to spin 3D too... > > > > Still, getting back to the site itself, it seems they > > > have a Stacked-die prototype path, and the main thrust is really mask- > > > asic. > > > > The stacked die 'emulation devices' will come at a large price > > > premium, and their config density will need to be low (given this is > > > top-layer stuff). > > > I'd expect a power premium too... > > > Stacked die? I read the eetimes article and didn't get anything about > > stacked die from Tier Logic. Did I read something wrong? I thought > > they were layering TFT on top of the base die to provide the config > > memory which takes it out of the base die saving real estate. > > Yes they are, which is why I called it stacked die. > - TWO die flows, one on top of the other. > > Base die is made, and then they have a second die-process that is > more complex than just TFT, as it > included connections. [Testing questions remain?] > > That will also be why they needed a lot more passes at the TFT > section, as that's where the 'new tech' mostly lies. Uh, "stacked die" is normally used to refer to putting two distinct die mechanically on top of each other. That is a very different thing than adding processing steps to an existing flow, which is what has been described for this part. > > They seem to be pushing their ability to more easily move to ASIC > > production, but they seem to offer something to the FPGA only user as > > well. > > A key question here will be: if you are unlikely to > need ASIC, why start with their devices ? They claim an advantage in die size which normally translates into a cost advantage. Of course, the question of cost will be answered when they start shipping product, or at least quoting prices. > > I'm not clear on what you are saying about this in regards to Tier Logic. > > It was a general comment, about where there is space for new-comers, > or new-products in the market. > > I've often found RAM dictates the Device choice, more than the Logic. I wish I had that luxury. For me it is typically package since my designs tend to be size constrained; low pin count (100 or less) in PCB layout and manufacturing friendly packages are always welcome (read that as TQFPs or possibly QFNs). Right now I am trying to squeeze 10 pounds of logic into a 5 pound FPGA because it was the only one that fit the bill, a bill that was designed a year and a half ago. Rick
From: -jg on 10 Mar 2010 18:14 On Mar 11, 11:29 am, rickman <gnu...(a)gmail.com> wrote: > On Mar 10, 4:54 pm, -jg <jim.granvi...(a)gmail.com> wrote: > > Yes they are, which is why I called it stacked die. > > - TWO die flows, one on top of the other. > > > Uh, "stacked die" is normally used to refer to putting two distinct > die mechanically on top of each other. That depends on where you are in the time-line :) Years ago, 'stacked die' meant post-wafer assembly using bond-wires & discrete die, but more modern "nailed stacked die" schemes use vias, and are done at the wafer level. ie See this fig2 of "nailed stacked die " here : http://www.flipchips.com/tutorial71.html and compare with the image here : http://www.tierlogic.com/uploads/press-room-files/Tier-Logic-Cross-Sections-of-TierFPGA-and-TierASIC-Devices.pdf The 'different process', and multiple Transistor planes, is now more a distinguishing feature, than a literal interpretation of 'die'. Tierlogic are quite clear they use Stacked (different) processes, and via type contacts. Doing the stacking at the wafer/fab level saves handling, but you are exposed to testing issues. Until you have finished the two-process flows, you really have nothing to test. So yields are ?? Default TFT flows are also higher voltage, and relatively coarse grained. So the bit-counts will be interestng to see, when they are finally revealed. -jg
From: Kim Enkovaara on 11 Mar 2010 01:45 austin wrote: > Except you require registration to even see what it is that you have. At least they don't require NDAs etc. for basic information. I don't see any problem in registration or even NDAs. A and X also require NDAs before they tell anything about their future products. > What are you afraid of? Competition? Possibly yes. The big guys are very happy to steal the good ideas of the smaller ones and use their muscle to push the innovations to their products, and the original inventor gets nothing (unless they vere good at patenting it). > So, until you decide to stop "qualifying customers" I am afraid you > will remain a relatively unknown company. A and X qualify also customers for early access etc. And for a small startup the qualifying is even more important, they don't have the muscle to support big amount of customers. > That is OK: the longer it takes for you to make money, the more > likely the investors pull the plug, and you go away like all the other > FPGA companies have in the past. The money is not in the hobbyist market but on the big accounts. And big accuounts have no problem with registration, NDAs etc. --Kim
From: Kim Enkovaara on 11 Mar 2010 01:54
-jg wrote: > Doing the stacking at the wafer/fab level saves handling, but you are > exposed to testing issues. > > Until you have finished the two-process flows, you really have > nothing to test. So yields are ?? I don't see it impossible to test the cmos wafer before the tft process, depending on how they constructed the topmost metal layer. For example they could have some dummy bump pads there for power, and then internal bist with certain coverage built with the lower metal layers. FPGAs are quite easy in terms of yield, because you can have redundant structures for yield improvement (in fabric and in memories). --Kim |