Tier Logic introduces the world's first 3D FPGA
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From: -jg on 11 Mar 2010 14:08 On Mar 12, 3:32 am, John_H <newsgr...(a)johnhandwork.com> wrote: > > The TierASIC is tested with a scan-based ASIC methodology we added to > > the silicon. The customer is not required to generate any test > > vectors. Once you lock your design, you simply send us the bitstream > > and we auto generate the test vectors for your ASIC. The claim of Auto-generate test vectors is interesting. Who pays for < 100% coverage 'issues' ? > While I can understand the savings brought from removing the > configuration memories and associated die size, I still envision the > FPGA-like overhead as being significant since routing is such a large > portion of typical FPGA resources. The memory has not gone away, in the FPGA flow is it merely stacked, so die size has shifted to more process steps. Raw silicon is actually quite cheap. Even in their ASIC flow, that 'memory ghost' remains, as the die size is locked to the larger of the two possible choices. Their fpga to asic step saving is some process steps, testing savings, and yield gains as they hope you are not using defects. Where die size savings really kick in, is when they allow MORE logic into what is a 'practical size ceiling' - but we still have no indications of WHO their customers are ? - no logic or package info ?. If your package is IO bound, then die size claims are totally illusory. -jg
From: Tier Logic on 11 Mar 2010 15:19 The extra processing steps for the TFT do cost more. However, the die size reduction swamps that out to create a low cost FPGA. The ASIC gets rid of that extra cost and benefits from the yield improvement for an even lower cost solution. All I can tell you is come get a quote and we can save you money. Xilinx and Altera love all the skepticism here and want you to conitnue paying too much for your solutions. Regards, Jeff
From: Raymund Hofmann on 11 Mar 2010 16:37 On 11 Mrz., 21:19, Tier Logic <jeff.ka...(a)gmail.com> wrote: > The extra processing steps for the TFT do cost more. However, the die > size reduction swamps that out to create a low cost FPGA. The ASIC > gets rid of that extra cost and benefits from the yield improvement > for an even lower cost solution. > > All I can tell you is come get a quote and we can save you money. > Xilinx and Altera love all the skepticism here and want you to > conitnue paying too much for your solutions. Isnt the biggest area in FPGAs covered by routing (lines & switches) which are still present in Tier Logic? Anyway it looks interesting to me and i have registered to evaluate further... But one thing i am concerned with is design security of the programmable devices.
From: Peter Alfke on 11 Mar 2010 16:40 On Mar 11, 12:19 pm, Tier Logic <jeff.ka...(a)gmail.com> wrote: > > Xilinx and Altera love all the skepticism here and want you to > conitnue paying too much for your solutions. > > Regards, > > Jeff Jeff, you should be ashamed of that cheap shot, especially when Austin earlier today invited the audience to check out your alleged lower prices. I can understand when a newcomer is aggressive in his claims, and nebulous in his explanations. But do not get sarcastic and nasty. You still have a lot to prove before you can climb on a high horse. Peter Alfke
From: whygee on 11 Mar 2010 16:31
Hello, Tier Logic wrote: > All I can tell you is come get a quote and we can save you money. it is a curious statement ! I assume that you have been too long in "stealth mode". Now I tell you this : "show me your public price list, your products, demo boards, detailed datasheet and distributors. Then maybe I'll choose you for a project". I'll take the example of a competitor. SiliconBlue has maybe "slow" chips (according to only one test I did) but they got it almost right for the rest, at least for me : - decent development tool (not bloated) that installs easily on Linux AND Windows ! - datasheet and other informations, enough to understand how it is ticking inside so it can be used - at least one distributor that talks to anyone (even though the distributor is not large, at least it does its job and doesn't scare potential customers) - unit price that is decent is small quantities. - ultra-low power is a plus but not critical for me. And still it's not functional enough for me. Antti has developped for it and I'm curious. Now before you can save me money, try to beat SBt, and then... beat the others :-P The Actel ProAsic3 family is working very fine for me and wonder how it can be displaced. good luck, > Regards, > Jeff yg -- http://ygdes.com / http://yasep.org |