XST is driving me mad.
in [FPGA]
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From: johnp on 19 Jan 2010 09:02 I assume you're using the raw input clock for this reset logic? If you're using the DCM output clock, it will nver count since the DCM is reset. John Providenza
From: ghelbig on 19 Jan 2010 13:45
On Jan 19, 12:20 am, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> wrote: > On Mon, 18 Jan 2010 23:50:01 -0800 (PST), "jmi...(a)pop.net" wrote: > >> if (|DCM_Delay) begin > >What character is in front of DCM_Delay in that if statement? > > I hope it's a vertical bar, the reduction-OR operator; > that would make the test effectively "if (DCM_Delay != 0)" > (which would have been more readable anyway). > > The code looks OK to me. The counter DCM_Delay should > reset to 4'hf, count down to zero and then remain stuck at > zero until the next reset. DCM_Reset should go to zero > one clock after DCM_Delay reaches zero. > > Is there any chance that (a) the clock is not ticking, or > (b) reset is stuck high? > -- > Jonathan Bromley I take both clock and reset to debug pins. They are working as expected. More investigation reveals that none of the clocked processes are running. It's as if there's some big global signal that is holding every flop in reset. I've tried 10.1.3 and 11.1.4 - both behave badly. I'm running in Linux64 (ubuntu 9.10), and can't find the 'enable global reset' option to turn it off. I got here trying to debug a DCM power-on reset. I've gone as far as stripping the code down to this counter and a couple of latches. The clock is the input to the DCM, but I've removed the DCM completely to debug this counter. I've noticed two more strange XST things: 1) If I use 'reset' as an async reset _anywhere_, XST assumes that it's OK to use it everywhere. Including on instance where I coded it (reset) as the input to a d-flop, and XST wired it to an async preset. 2) If I connect the counter to debug pins without a name translation or an OBUF, XST will disconnect the counter from the net. Looking at the RTL (or technology) schematic shows the output of the counter dangling. Frustrated, Gary. Comment on #1 above: The code is always @ (posedge fpga_clock) reset_d <= reset; XST ties the D input to '0', and connects reset to the async preset! |