Xilinx and Multi-port memories
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From: rickman on 28 Dec 2009 11:53 On Dec 28, 3:40 am, whygee <y...(a)yg.yg> wrote: > hello, > > Amal wrote: > > Xilinx supports 3-port memories as well if it helps. You can have one > > read/write port and two read ports with 3 different addresses. > > You can either infer it or instantiate the component directly. > > the OP and the thread are speaking about multiple write port, > because multiple read ports are trivially implemented. > However, simultaneously having 2 read AND 2 write ports > (4 simultaneous addresses, for example) is not as easy > and I guess that few synthesisers will infer the correct > SRAM blocks. The OP doesn't need four ports from a single memory, only three are needed. If two write ports are needed, there is no way to fake that, at least no easy way. Three ports are needed, two write and one read. Then as many read ports can be added as needed by duplicating the memory with separate read addresses. If the OP can use the same address for one write port and the read port, then this is just a two port memory with read/write capability. If a two write, one read port memory with three addresses is needed and only two addresses can be input to the memory, then a third memory can be used to "arbitrate" between two duplicated, two address, one write, one read port memories. When a write happens, the data is written to the memory connected to that write port. The third memory is just one bit wide and the bit at the corresponding address is set or reset to indicate which port the most recent write has been from. When a read is done, a mux selects from the appropriate memory block. The only fly in the ointment is that the "flag" memory has to have two write and two read ports. So it can't be done in a block ram, but must be made of logic and FFs. That is some savings over doing the entire memory in logic if it is wider than one bit... but still a PITA and quite a mess. But if you *have* to have this memory and the part does not support it... I guess you have no choice, eh? Rick
From: Selensky on 29 Dec 2009 10:07 On 28 dez, 04:17, Amal <akhailt...(a)gmail.com> wrote: > On Dec 26, 3:14 pm, Muzaffer Kal <k...(a)dspia.com> wrote: > > > > > On Fri, 25 Dec 2009 21:38:48 -0700, Rob Doyle <radioe...(a)gmail.com> > > wrote: > > > >If I *had* to add another write port to the memory - can you do that > > >using memories? I can't see it... > > > One thing you can do is to have two copies of your register file and > > keep a 'most-recently-written' state for each location. Then each read > > path has an additional 2-1 mux after it controlled by the same signal > > (and a comparator for the read address). This should give the datapath > > you want but whether the extra delay is acceptable depends on your > > requirements. > > -- > > Muzaffer Kal > > > DSPIA INC. > > ASIC/FPGA Design Services > > >http://www.dspia.com > > Xilinx supports 3-port memories as well if it helps. You can have one > read/write port and two read ports with 3 different addresses. > > You can either infer it or instantiate the component directly. > > Cheers, > -- Amal Amal, Are native 3-port mode supported by which Xilinx devices? Without duplicating memories? Is there any constraint about using this operation mode combined with different aspect data ratio? I had heard something about native support of 3-port (two read and one write port with 3 different addresses) in Altera devices only. Selensky
From: Rob Doyle on 29 Dec 2009 16:37 rickman wrote: > On Dec 28, 3:40 am, whygee <y...(a)yg.yg> wrote: >> hello, >> >> Amal wrote: >>> Xilinx supports 3-port memories as well if it helps. You can have one >>> read/write port and two read ports with 3 different addresses. >>> You can either infer it or instantiate the component directly. >> the OP and the thread are speaking about multiple write port, >> because multiple read ports are trivially implemented. >> However, simultaneously having 2 read AND 2 write ports >> (4 simultaneous addresses, for example) is not as easy >> and I guess that few synthesisers will infer the correct >> SRAM blocks. > > The OP doesn't need four ports from a single memory, only three are > needed. If two write ports are needed, there is no way to fake that, > at least no easy way. Three ports are needed, two write and one > read. Then as many read ports can be added as needed by duplicating > the memory with separate read addresses. If the OP can use the same > address for one write port and the read port, then this is just a two > port memory with read/write capability. > > If a two write, one read port memory with three addresses is needed > and only two addresses can be input to the memory, then a third memory > can be used to "arbitrate" between two duplicated, two address, one > write, one read port memories. When a write happens, the data is > written to the memory connected to that write port. The third memory > is just one bit wide and the bit at the corresponding address is set > or reset to indicate which port the most recent write has been from. > When a read is done, a mux selects from the appropriate memory block. > The only fly in the ointment is that the "flag" memory has to have two > write and two read ports. So it can't be done in a block ram, but > must be made of logic and FFs. That is some savings over doing the > entire memory in logic if it is wider than one bit... but still a PITA > and quite a mess. But if you *have* to have this memory and the part > does not support it... I guess you have no choice, eh? > > Rick I *need* one write port and three read ports - so I'm OK just duplicating the RAM. I could save a clock cycle in the ALU if I could do two writes and three reads. If I have to stall the pipeline to implement this, I've gained nothing. The timing won't permit 2 Register clock cycles per ALU clock cycle to double-up the register accesses. The multi-port "flag" memory is the trick I was looking for. The ALU has 1024 registers so I can envision some tall data selectors, multiplexers, and accompanying levels of logic to implement the address decoders. I think I'm going to stay with simple for now and put this in my back pocket as "Plan B". I greatly appreciate the help. Rob Doyle
From: Brian Drummond on 29 Dec 2009 19:16 On Tue, 29 Dec 2009 14:37:18 -0700, Rob Doyle <radioengr(a)gmail.com> wrote: >rickman wrote: >> On Dec 28, 3:40 am, whygee <y...(a)yg.yg> wrote: >>> hello, >>> >>> Amal wrote: >>>> Xilinx supports 3-port memories as well if it helps. You can have one >>>> read/write port and two read ports with 3 different addresses. >I could save a clock cycle in the ALU if I could do two writes >and three reads. If I have to stall the pipeline to implement >this, I've gained nothing. > >The timing won't permit 2 Register clock cycles per ALU clock cycle >to double-up the register accesses. > >The multi-port "flag" memory is the trick I was looking for. The ALU >has 1024 registers so I can envision some tall data selectors, >multiplexers, and accompanying levels of logic to implement the >address decoders. Another trick, IF you have some control over the instruction set, is to split the register set in two. Then you can schedule two writes, provided they are to different halves. (The read side can appear as a single unified regset) With the large number of registers a BRAM gives you, it is likely that there will always be "vacant" slots in each half. So this restriction can usually be hidden by register allocation policy, if you get to dictate such restrictions to whoever is writing the code generator. Essentially you trade simpler hardware for some additional complexity in software; the compiler writers make that invisible to the user. - Brian
From: John_H on 1 Jan 2010 18:13
On Dec 29 2009, 10:07 am, Selensky <selen...(a)gmail.com> wrote: > > Are native 3-port mode supported by which Xilinx devices? Without > duplicating memories? Is there any constraint about using this > operation mode combined with different aspect data ratio? I had heard > something about native support of 3-port (two read and one write port > with 3 different addresses) in Altera devices only. > > Selensky Any good synthesizer can take one memory array with one write and multiple reads and effectively replicate the memories without manual intervention from the user. As long as the memory inferences are written in a way which properly instantiates one memory, having multiple reads inferred in the same "structure" automatically replicates the memories delivering post-synthesis names for the memory elements that are slightly different. |