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From: colin on 16 Jul 2010 09:25
On 16 July, 11:42, "salimbaba"
<a1234573(a)n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Another thing, when the FPGA 2 gets programmed and i read its status
> register, it looks perfectly in accordance to a working FPGA's status word
> but it doesn't show any output. Is it possible that FPGA 2 never comes out
> of the startup sequunce ?
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

On the face of it your having the same results as I had and it was all
straightforward. An unprogrammed FPGA drives done low using open
drain. When you program them they fail at the very last point " I am
now programmed, I have released done but done is still low so I will
not start working". All I did was programmed each FPGA using JTAG but
only when you program the last FPGA does done go high and the FPGA
starts. Done is now not being driven low by anything and programming
any FPGA will make it work.

Typing "done pin" at xilinx.com and selecting the first hit explains
this fairly well.

Colin
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