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From: salimbaba on 15 Jul 2010 03:11
Hello!
I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain
on a custom board. The problem is when i program my FPGAs through JTAG
interface, FPGA 1 always gets programmed and verified and always shows
output whereas FPGA 2 always gets programmed and verified and sometimes it
shows the output and sometimes it doesnt.

I have failed to understand the reason for this behavior :s

Kindly help me .. thanks

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From: John_H on 15 Jul 2010 18:36
On Jul 15, 3:11 am, "salimbaba"
<a1234573(a)n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Hello!
> I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain
> on a custom board. The problem is when i program my FPGAs through JTAG
> interface, FPGA 1 always gets programmed and verified and always shows
> output whereas FPGA 2 always gets programmed and verified and sometimes it
> shows the output and sometimes it doesnt.
>
> I have failed to understand the reason for this behavior :s
>
> Kindly help me .. thanks          
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

Do you always program them in sequence after power-up?

If you randomly reprogram the devices well after the initial program,
you could be getting trouble from an open-drain configuration I/O pin
connected in common between the two chips. To program chips in a
chain independently after power up in the Xilinx chain I used a couple
years back, assertion of the program pin causes the done pin to go low
which confuses the other chip as an input.
From: salimbaba on 16 Jul 2010 05:18
Yes i always program it in a sequence i.e. FPGA 1 and then FPGA 2.
another point i missed in the last post is that while programming FPGA 1, i
give it the bit file with DRIVE DONE = YES, and when i program FPGA 2 , i
give it the bit file with DRIVE DONE = YES.

When i give FPGA 1 the bit file with DRIVE DONE = NO, it doesn't get
programmed and FPGA 2 shows the same random behavior as mentioned above.
and when i reprogram FPGA 1 after FPGA 2 , FPGA 1 gets programmed. Now,
there's something fishy going around with the DONE signal i guess, but i'm
not sure about it so i need pointers, help, anything that would give a
lead.

Thanks John =)

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From: John_H on 16 Jul 2010 06:27
On Jul 16, 5:18 am, "salimbaba"
<a1234573(a)n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
<snip>
>
> there's something fishy going around with the DONE signal i guess, but i'm
> not sure about it so i need pointers, help, anything that would give a
> lead.
>
> Thanks John =)    

Read up on the DONE signal and its effect as an *input* to the FPGA.

Note that it gets pulled down (regardless of drive=yes or no, I
believe) when the program bit is first asserted. One way to avoid
this interaction is to break out the done separately from the two
FPGAs so the open-drain pull-down of the DONE signal on one device
doesn't affect the operation of the second; rather than one DONE
connection to your programming device (assuming you're not programming
via cable) you use two.

Also look at whether DRIVE DONE = YES actively tries to assert the
DONE pin even if the DONE from the other chip drives the same line
with a typically-stronger pull down. Typical use is to have the DONE
pulled up with a resistor and leave the rising edge for when all
devices are programmed. The DRIVE DONE = YES would be for non-ganged
DONE pins such as a single FPGA or separately pinned out DONE signals
for the individual FPGAs so you don't have to add the pull-up to the
single driver.
From: salimbaba on 16 Jul 2010 06:42
Another thing, when the FPGA 2 gets programmed and i read its status
register, it looks perfectly in accordance to a working FPGA's status word
but it doesn't show any output. Is it possible that FPGA 2 never comes out
of the startup sequunce ?


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