Formula for minimum drive current for mosfet
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From: Jon Slaughter on 12 Apr 2008 16:33 BTW, this should point to an optimal switching frequency for least power dissipation? Anyone know the formula?
From: Jon Slaughter on 12 Apr 2008 17:26 "gearhead" <nospam(a)billburg.com> wrote in message news:7e10d5cc-4430-45df-8654-c9ace3961ffa(a)x41g2000hsb.googlegroups.com... On Apr 10, 4:44 pm, Fred Bloggs <nos...(a)nospam.com> wrote: > bill.slo...(a)ieee.org wrote: > > On 11 apr, 01:33, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: > > >>Whats the formula? > > >>I = 1/2*F*Q*V? > > >>Trying to figure out if I can drive > > >>http://www.fairchildsemi.com/pf/FD/FDD8424H.html > > >>with a uC directly? (I think it can supply up to 20mA or so) > > >>V = 12V if I use pullup and 5V if not. > > > Check out the data sheet. Figure 7 shows the typical gate charge > > required to get the gate voltage up to a level where the part is > > turned on - something like 10nC. The worst case total gate charge > > listed earlier in the data sheet is 24uC. > > > 20mA s going to take 1.2usec to deliver that 24uC of charge - this is > > slow switching by MOSFET standards, and you won't want to switch that > > slowly very often, because if you do there is a real risk that the > > switch will overheat. > > > -- > > Bill Sloman, Nijmegen > > That thing looks like a cross conduction hazard and half at that > switching speed, both FETs come on at less than 2V from their source > rails, wonder if he's tying the gates together, definitely would want to > switch as fast as possible then...- Hide quoted text - > > - Show quoted text - > Jon, the problem is the amount of time it takes the mosfet(s) to > transition from on to off and back from off to on again. During each > switching action of a mosfet it acts like a resistor for the > duration. Heat! So you want the duration of each switching event as > short as possible, regardless of whether these events occur at 100Hz > or 100kHz. Its not so simple. I do see that now as I stated in the last post I made. I thought when they said frequency they meant something else and not the switchign time. (although you do make it much clearer than they did) But I cannot switch at any frequency and have as fast a transition as I want. I must drive the gates of the mosfet with BJT's and, of course, they have there own limits. > But that's only part of the problem. Fred brings up a good point > about cross-conduction. > Now, when your drive has the gates pulled all the way to the rail > (either one), that's no problem. > But it IS a problem during the switching transition, because both > mosfets are partly turned on providing a path -- not through the load, > but directly across the power rails. You don't want slow switching > here. Yes, I know.. its basically just like CMOS(I guess it is CMOS) and there is a short between tranistions. But there are a few solutions. One is to switch the mosfets on sequentially instead of at the same time. Al I loose is a bit of power to the motor momentarily but inertia should smooth it out. (basically delay the PWM a bit until the transition of the first fet is finished) But you do make a good point. The problem is, I do have limitations. I do see bill's point now about using a uC to drive the fets as its probably just way to low. Ultimately I'd like a formula for drive. (is it a simple RC circuit(Approximately) or more?) > So a weak drive is bad. > For motor drive, a kilohertz is probably way plenty, and this lower > frequency is better so that you don't put your mosfets in the hot seat > so often. Well, I do understand that(and its more clear now that you said it). The thing about that slow of a frequency, from what I've read, is that its audiable(Which may or may not be an issue depending on how loud it is). Basically I need to maximize transition time and minimize frequency given all the contraints. (> 20khz(probably), surge current by drivers(bjt's), least power dissipation(Although I guess as long as its below max I'm ok)). Ok, I guess I see the confusion. The subject is minimum drive current for mosfets. I guess this is bad. I shouldn't require a minimum but a maxium within the mosfet drivers specs. (basically what I wanted was a formula to see the relationship) What I plan on doing is use bjt's to drive the gates in emitter follower... but I need to configure them for optimal conditions. (max drive current but within device specs) Anyways, thanks for the post. Its more clear now but I need to let it settle in. (I "knew" all the concepts before but there was just no glue tieing them together ;/) (Although I'd still like to drive them with the uC if possible because that is the simplest method... sure it might not be most efficient but if I'm still able to get reasonble power dissipation then its not *wrong* but just not optimal) Thanks, Jon
From: Jon Slaughter on 12 Apr 2008 17:32 > > Its not so simple. I do see that now as I stated in the last post I made. > I thought when they said frequency they meant something else and not the > switchign time. (although you do make it much clearer than they did) Basically what I'm saying is, is that my drive can supply a surge current of X, I need to know how much power dissipation this gives. I know ultimately I'd want to supply as much as possible but, for example, I can't supply 15A because it has to go through the bjt and then I'll have to worry about power dissipation in that. (I also don't want to run the BJT's at max to get that current) I suppose I could use some other mosfets to drive the gates but seems like eventually I'll have diminishing returns?
From: bill.sloman on 12 Apr 2008 20:40 On 12 apr, 22:33, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: > BTW, this should point to an optimal switching frequency for least power > dissipation? Anyone know the formula? The less frequently you switch your transistors, the less energy gets dumped into them, so you minimise switching losses by not switching. You don't need a formula to know that. There isn't much point in getting the power being lost in switching the transistors (dynamic losses) much below the power being dissipated in the transistors all the time there is current flowing through them (static losses). You've still got to heat sink the transistors well enough to get rid of the heat generated by the static losses, so you may well choose to have enough switching events per second so that your dynamic losses are about the same as your static losses. This makes for smaller and cheaper inductors and capacitors in your output filter than you'd need with fewer switching events. As you push the switching frequency higher you have to balance the need for bigger heat-sinks on your switches against further reductions in the size of the inductors and capacitors in the output filter. -- Bill Sloman, Nijmegen
From: miso on 12 Apr 2008 21:58
On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: > BTW, this should point to an optimal switching frequency for least power > dissipation? Anyone know the formula? There is a point where the transistor no longer sees average power but peak power. Never having designed in a power fet process, I don't know the design rule. In more general purpose semiconductor processes, the electromigration frequency limit is 1Khz. That is, a line that is being pulsed that you wish to consider receiving average current should be switching faster that 1KHz. Power MOSFETs do have SOA limits, but it is not as critical as with bipolars. I like how you worry about everything. No, really. ;-) There is noting worse than getting product returned. If your intent is to drive directly from the uP, you may want to consider how the load switching will effect the uP. You will probably get ground bounce. In addition, as you increase VGS, there will be current flow from CDG. If the drain voltage is falling like a rock, it will generate current that opposes your gate drive. What I'm leading to here is you should probably buffer the uP from the power fet. |