Formula for minimum drive current for mosfet
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From: Paul E. Schoen on 12 Apr 2008 22:54 <miso(a)sushi.com> wrote in message news:3e667771-ed64-4a9e-a065-ced0e13f718f(a)k1g2000prb.googlegroups.com... > On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: >> BTW, this should point to an optimal switching frequency for least power >> dissipation? Anyone know the formula? > > There is a point where the transistor no longer sees average power but > peak power. Never having designed in a power fet process, I don't know > the design rule. In more general purpose semiconductor processes, the > electromigration frequency limit is 1Khz. That is, a line that is > being pulsed that you wish to consider receiving average current > should be switching faster that 1KHz. > > Power MOSFETs do have SOA limits, but it is not as critical as with > bipolars. > > I like how you worry about everything. No, really. ;-) There is noting > worse than getting product returned. > > If your intent is to drive directly from the uP, you may want to > consider how the load switching will effect the uP. You will probably > get ground bounce. In addition, as you increase VGS, there will be > current flow from CDG. If the drain voltage is falling like a rock, it > will generate current that opposes your gate drive. What I'm leading > to here is you should probably buffer the uP from the power fet. I just finished looking into various MOSFET gate drivers for my design. They generally cost less than a dollar, and they really switch capacitive loads quickly, which cuts the switching losses quite a bit. Some good drivers from National, Maxim, TI, and Microchip are: TPS2819 LM5112 MCP1415 MAX5048 TC1413 TC4421 UCC27321/2 UC3710 I also played around with a homebrew MOSFET driver using an NPN and PNP transistor, and a few resistors and diodes, and it seemed to work pretty well in the simulator. I also set it up with a bootstrap to the MOSFET drain, with the idea that maybe a driver could be built into a MOSFET, but it's probably better to tie the voltage supply for the driver to a 5 volt or 12 volt supply. So you can omit some of this circuitry, but it is probably a good idea to have some sort of limiting resistor. I tried a simpler driver with an NPN and PNP with bases tied together as the input and emitters tied together as the output, with collectors across a 12 volt supply, and somehow there was simultaneous conduction and one of the transistors popped. Probably because they were not well matched. So here's a circuit you can try: Paul ==================================================================================== Version 4 SHEET 1 880 680 WIRE 240 16 -384 16 WIRE 32 64 -176 64 WIRE 240 64 240 16 WIRE 32 80 32 64 WIRE 208 80 176 80 WIRE 32 96 32 80 WIRE -448 144 -512 144 WIRE -176 144 -176 64 WIRE -176 144 -448 144 WIRE -32 144 -96 144 WIRE 208 160 208 80 WIRE 240 160 240 144 WIRE 240 160 208 160 WIRE -384 192 -384 16 WIRE -272 240 -304 240 WIRE -112 240 -128 240 WIRE -96 240 -96 144 WIRE -96 240 -112 240 WIRE -16 240 -32 240 WIRE 32 240 32 192 WIRE 32 240 -16 240 WIRE 64 240 32 240 WIRE 192 240 64 240 WIRE -512 256 -512 144 WIRE -448 256 -448 144 WIRE -304 272 -304 240 WIRE -112 272 -112 240 WIRE 64 272 64 240 WIRE 240 272 240 256 WIRE -16 288 -16 240 WIRE -192 320 -192 240 WIRE -176 320 -192 320 WIRE -512 400 -512 320 WIRE -448 400 -448 320 WIRE -448 400 -512 400 WIRE -384 400 -384 272 WIRE -384 400 -448 400 WIRE -304 400 -304 352 WIRE -304 400 -384 400 WIRE -192 400 -304 400 WIRE -112 400 -112 368 WIRE -112 400 -192 400 WIRE -16 400 -16 352 WIRE -16 400 -112 400 WIRE 64 400 64 352 WIRE 64 400 -16 400 WIRE 240 400 240 352 WIRE 240 400 64 400 FLAG -304 240 Vin FLAG -16 240 Vgate FLAG -16 400 0 SYMBOL voltage -304 256 R0 WINDOW 3 -95 172 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 WINDOW 0 36 57 Left 0 SYMATTR Value PULSE(0 5 50u 50n 10n 5u 10u 100) SYMATTR InstName V1 SYMBOL res -176 224 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 200 SYMBOL cap -32 288 R0 SYMATTR InstName C1 SYMATTR Value 3800p SYMBOL nmos 192 160 R0 SYMATTR InstName M1 SYMATTR Value SUM75N06-09L SYMBOL res 224 48 R0 SYMATTR InstName R2 SYMATTR Value 2 SYMBOL voltage -384 176 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL res 224 256 R0 SYMATTR InstName R3 SYMATTR Value .05 SYMBOL npn -32 96 R0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL schottky -32 224 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName D1 SYMATTR Value 1N5818 SYMATTR Description Diode SYMATTR Type diode SYMBOL res 48 256 R0 SYMATTR InstName R4 SYMATTR Value 4.7k SYMBOL pnp -176 368 M180 SYMATTR InstName Q2 SYMATTR Value 2N3906 SYMBOL res -80 128 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R5 SYMATTR Value 5k SYMBOL res -176 416 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R6 SYMATTR Value 5k SYMBOL schottky -192 224 M90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName D2 SYMATTR Value 1N5818 SYMATTR Description Diode SYMATTR Type diode SYMBOL cap -464 256 R0 SYMATTR InstName C2 SYMATTR Value 100n SYMATTR SpiceLine V=16 Irms=0 Rser=0.007 MTBF=0 Lser=0 ppPkg=1 SYMBOL schottky 96 64 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName D3 SYMATTR Value 1N5818 SYMATTR Description Diode SYMATTR Type diode SYMBOL zener -496 320 R180 WINDOW 0 24 72 Left 0 WINDOW 3 24 0 Left 0 SYMATTR InstName D4 SYMATTR Value BZX84C12L SYMATTR Description Diode SYMATTR Type diode SYMBOL res 192 64 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R7 SYMATTR Value 200 TEXT -304 464 Left 0 !.tran 0 1m 0 startup
From: gearhead on 13 Apr 2008 00:18 On Apr 12, 7:54 pm, "Paul E. Schoen" <pst...(a)smart.net> wrote: > <m...(a)sushi.com> wrote in message > > news:3e667771-ed64-4a9e-a065-ced0e13f718f(a)k1g2000prb.googlegroups.com... > > On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: > >> BTW, this should point to an optimal switching frequency for least power > >> dissipation? Anyone know the formula? > (snip) > > If your intent is to drive directly from the uP, you may want to > > consider how the load switching will effect the uP. You will probably > > get ground bounce. In addition, as you increase VGS, there will be > > current flow from CDG. If the drain voltage is falling like a rock, it > > will generate current that opposes your gate drive. What I'm leading > > to here is you should probably buffer the uP from the power fet. > > I just finished looking into various MOSFET gate drivers for my design. (snip) > I also played around with a homebrew MOSFET driver using an NPN and PNP > transistor, and a few resistors and diodes, and it seemed to work pretty > well in the simulator. I also set it up with a bootstrap to the MOSFET > drain, with the idea that maybe a driver could be built into a MOSFET, but > it's probably better to tie the voltage supply for the driver to a 5 volt > or 12 volt supply. So you can omit some of this circuitry, but it is > probably a good idea to have some sort of limiting resistor. I tried a > simpler driver with an NPN and PNP with bases tied together as the input > and emitters tied together as the output, with collectors across a 12 volt > supply, and somehow there was simultaneous conduction and one of the > transistors popped.> Paul > Did you use a resistors in each base, or just tie them together?
From: Paul E. Schoen on 13 Apr 2008 03:40 "gearhead" <nospam(a)billburg.com> wrote in message news:be00fe5b-5dc3-420f-8f1b-07643cb42a5a(a)e39g2000hsf.googlegroups.com... On Apr 12, 7:54 pm, "Paul E. Schoen" <pst...(a)smart.net> wrote: > <m...(a)sushi.com> wrote in message > > news:3e667771-ed64-4a9e-a065-ced0e13f718f(a)k1g2000prb.googlegroups.com... > > On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: > >> BTW, this should point to an optimal switching frequency for least > >> power > >> dissipation? Anyone know the formula? > (snip) > > If your intent is to drive directly from the uP, you may want to > > consider how the load switching will effect the uP. You will probably > > get ground bounce. In addition, as you increase VGS, there will be > > current flow from CDG. If the drain voltage is falling like a rock, it > > will generate current that opposes your gate drive. What I'm leading > > to here is you should probably buffer the uP from the power fet. > > I just finished looking into various MOSFET gate drivers for my design. (snip) > I also played around with a homebrew MOSFET driver using an NPN and PNP > transistor, and a few resistors and diodes, and it seemed to work pretty > well in the simulator. I also set it up with a bootstrap to the MOSFET > drain, with the idea that maybe a driver could be built into a MOSFET, > but > it's probably better to tie the voltage supply for the driver to a 5 volt > or 12 volt supply. So you can omit some of this circuitry, but it is > probably a good idea to have some sort of limiting resistor. I tried a > simpler driver with an NPN and PNP with bases tied together as the input > and emitters tied together as the output, with collectors across a 12 > volt > supply, and somehow there was simultaneous conduction and one of the > transistors popped.> Paul > Did you use a resistors in each base, or just tie them together? >>>>>>>>>>>>>>>>>> I just tied them together. It's basically two emitter followers. They should never be both on at the same time, but if one is slower than the other, I guess it can happen, and did. The simulation looked OK. Paul
From: Fred Bloggs on 13 Apr 2008 08:35 Paul E. Schoen wrote: > probably a good idea to have some sort of limiting resistor. I tried a > simpler driver with an NPN and PNP with bases tied together as the input > and emitters tied together as the output, with collectors across a 12 volt > supply, and somehow there was simultaneous conduction and one of the > transistors popped. I just don't see how that's possible unless your input drive was so blindingly fast and there were enough parasitics to avalanche a BE junction at a transition. Ordinarily there can be no crossconduction when the forward BE voltage on the one transistor is a cut-off reverse BE bias for the other... > Probably because they were not well matched. So here's > a circuit you can try: > > Paul What in the world is all that, and why all that gate capacitance: > > ==================================================================================== > > Version 4 > SHEET 1 880 680 > WIRE 240 16 -384 16 > WIRE 32 64 -176 64 > WIRE 240 64 240 16 > WIRE 32 80 32 64 > WIRE 208 80 176 80 > WIRE 32 96 32 80 > WIRE -448 144 -512 144 > WIRE -176 144 -176 64 > WIRE -176 144 -448 144 > WIRE -32 144 -96 144 > WIRE 208 160 208 80 > WIRE 240 160 240 144 > WIRE 240 160 208 160 > WIRE -384 192 -384 16 > WIRE -272 240 -304 240 > WIRE -112 240 -128 240 > WIRE -96 240 -96 144 > WIRE -96 240 -112 240 > WIRE -16 240 -32 240 > WIRE 32 240 32 192 > WIRE 32 240 -16 240 > WIRE 64 240 32 240 > WIRE 192 240 64 240 > WIRE -512 256 -512 144 > WIRE -448 256 -448 144 > WIRE -304 272 -304 240 > WIRE -112 272 -112 240 > WIRE 64 272 64 240 > WIRE 240 272 240 256 > WIRE -16 288 -16 240 > WIRE -192 320 -192 240 > WIRE -176 320 -192 320 > WIRE -512 400 -512 320 > WIRE -448 400 -448 320 > WIRE -448 400 -512 400 > WIRE -384 400 -384 272 > WIRE -384 400 -448 400 > WIRE -304 400 -304 352 > WIRE -304 400 -384 400 > WIRE -192 400 -304 400 > WIRE -112 400 -112 368 > WIRE -112 400 -192 400 > WIRE -16 400 -16 352 > WIRE -16 400 -112 400 > WIRE 64 400 64 352 > WIRE 64 400 -16 400 > WIRE 240 400 240 352 > WIRE 240 400 64 400 > FLAG -304 240 Vin > FLAG -16 240 Vgate > FLAG -16 400 0 > SYMBOL voltage -304 256 R0 > WINDOW 3 -95 172 Left 0 > WINDOW 123 0 0 Left 0 > WINDOW 39 0 0 Left 0 > WINDOW 0 36 57 Left 0 > SYMATTR Value PULSE(0 5 50u 50n 10n 5u 10u 100) > SYMATTR InstName V1 > SYMBOL res -176 224 R90 > WINDOW 0 0 56 VBottom 0 > WINDOW 3 32 56 VTop 0 > SYMATTR InstName R1 > SYMATTR Value 200 > SYMBOL cap -32 288 R0 > SYMATTR InstName C1 > SYMATTR Value 3800p > SYMBOL nmos 192 160 R0 > SYMATTR InstName M1 > SYMATTR Value SUM75N06-09L > SYMBOL res 224 48 R0 > SYMATTR InstName R2 > SYMATTR Value 2 > SYMBOL voltage -384 176 R0 > WINDOW 123 0 0 Left 0 > WINDOW 39 0 0 Left 0 > SYMATTR InstName V2 > SYMATTR Value 12 > SYMBOL res 224 256 R0 > SYMATTR InstName R3 > SYMATTR Value .05 > SYMBOL npn -32 96 R0 > SYMATTR InstName Q1 > SYMATTR Value 2N3904 > SYMBOL schottky -32 224 R90 > WINDOW 0 0 32 VBottom 0 > WINDOW 3 32 32 VTop 0 > SYMATTR InstName D1 > SYMATTR Value 1N5818 > SYMATTR Description Diode > SYMATTR Type diode > SYMBOL res 48 256 R0 > SYMATTR InstName R4 > SYMATTR Value 4.7k > SYMBOL pnp -176 368 M180 > SYMATTR InstName Q2 > SYMATTR Value 2N3906 > SYMBOL res -80 128 R90 > WINDOW 0 0 56 VBottom 0 > WINDOW 3 32 56 VTop 0 > SYMATTR InstName R5 > SYMATTR Value 5k > SYMBOL res -176 416 R180 > WINDOW 0 36 76 Left 0 > WINDOW 3 36 40 Left 0 > SYMATTR InstName R6 > SYMATTR Value 5k > SYMBOL schottky -192 224 M90 > WINDOW 0 0 32 VBottom 0 > WINDOW 3 32 32 VTop 0 > SYMATTR InstName D2 > SYMATTR Value 1N5818 > SYMATTR Description Diode > SYMATTR Type diode > SYMBOL cap -464 256 R0 > SYMATTR InstName C2 > SYMATTR Value 100n > SYMATTR SpiceLine V=16 Irms=0 Rser=0.007 MTBF=0 Lser=0 ppPkg=1 > SYMBOL schottky 96 64 R90 > WINDOW 0 0 32 VBottom 0 > WINDOW 3 32 32 VTop 0 > SYMATTR InstName D3 > SYMATTR Value 1N5818 > SYMATTR Description Diode > SYMATTR Type diode > SYMBOL zener -496 320 R180 > WINDOW 0 24 72 Left 0 > WINDOW 3 24 0 Left 0 > SYMATTR InstName D4 > SYMATTR Value BZX84C12L > SYMATTR Description Diode > SYMATTR Type diode > SYMBOL res 192 64 R90 > WINDOW 0 0 56 VBottom 0 > WINDOW 3 32 56 VTop 0 > SYMATTR InstName R7 > SYMATTR Value 200 > TEXT -304 464 Left 0 !.tran 0 1m 0 startup > >
From: gearhead on 13 Apr 2008 14:24
On Apr 13, 12:40 am, "Paul E. Schoen" <pst...(a)smart.net> wrote: > "gearhead" <nos...(a)billburg.com> wrote in message > > news:be00fe5b-5dc3-420f-8f1b-07643cb42a5a(a)e39g2000hsf.googlegroups.com... > On Apr 12, 7:54 pm, "Paul E. Schoen" <pst...(a)smart.net> wrote:> <m...(a)sushi.com> wrote in message > > >news:3e667771-ed64-4a9e-a065-ced0e13f718f(a)k1g2000prb.googlegroups.com... > > > On Apr 12, 1:33 pm, "Jon Slaughter" <Jon_Slaugh...(a)Hotmail.com> wrote: > > >> BTW, this should point to an optimal switching frequency for least > > >> power > > >> dissipation? Anyone know the formula? > > (snip) > > > > If your intent is to drive directly from the uP, you may want to > > > consider how the load switching will effect the uP. You will probably > > > get ground bounce. In addition, as you increase VGS, there will be > > > current flow from CDG. If the drain voltage is falling like a rock, it > > > will generate current that opposes your gate drive. What I'm leading > > > to here is you should probably buffer the uP from the power fet. > > > I just finished looking into various MOSFET gate drivers for my design. > > (snip) > > > I also played around with a homebrew MOSFET driver using an NPN and PNP > > transistor, and a few resistors and diodes, and it seemed to work pretty > > well in the simulator. I also set it up with a bootstrap to the MOSFET > > drain, with the idea that maybe a driver could be built into a MOSFET, > > but > > it's probably better to tie the voltage supply for the driver to a 5 volt > > or 12 volt supply. So you can omit some of this circuitry, but it is > > probably a good idea to have some sort of limiting resistor. I tried a > > simpler driver with an NPN and PNP with bases tied together as the input > > and emitters tied together as the output, with collectors across a 12 > > volt > > supply, and somehow there was simultaneous conduction and one of the > > transistors popped.> Paul > > Did you use a resistors in each base, or just tie them together? > > > > I just tied them together. It's basically two emitter followers. They > should never be both on at the same time, but if one is slower than the > other, I guess it can happen, and did. The simulation looked OK. > > Paul I haven't tried to use that totem pole myself, but I remember reading a comment somewhere by somebody that used two such totem poles in an H- bridge setup to drive a motor and said he had to use base resistors to avoid problems. The writer evinced some mystification as to why it should be so, but empirics rule! Fred is correct that in principle, you can't bias both transistors on simultaneously in that topology. Something else happened. Perhaps the transistors oscillated, and some parasitic effect may made it even worse. Base resistors would damp that. I think a little capacitance between base and collector will help tame high-strung behaviour as well. |