How do you design these days?
in [Design]
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From: Joerg on 5 Jan 2010 13:52 John Larkin wrote: > On Mon, 4 Jan 2010 20:22:14 -0800, "Joel Koltner" > <zapwireDASHgroups(a)yahoo.com> wrote: > >> "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >> news:hfa5k51hc8fad9u8b0dpqbae43p4lekho8(a)4ax.com... >>> You haven't worked with The Brat. >> I've never even worked with a layout woman. Heck, not even any female >> hardware designers... although a few female programmers. (And one claimed to >> have done digital hardware design at a PPOE...) > > > The best two layout-ers I've worked with pre-Brat were women. > Same here. The first one drove a souped-up Z28, Mario Andretti style. > I've never worked with a full-time female circuit designer, or even > met one to my knowledge. ... I've worked with one that did switch-mode supply designs, something most engineers seem not to enjoy at all. Note to readers: Too late, she's now married. [...] -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
From: krw on 5 Jan 2010 18:36 On Tue, 5 Jan 2010 10:17:34 -0800, "Joel Koltner" <zapwireDASHgroups(a)yahoo.com> wrote: >"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >news:2nh5k59u7thoqc6pvaassqbcrkvv0hcb34(a)4ax.com... >> Sure, will do when it's presentable. Additions are welcome. > >Great, thanks John. > >> We draw it with PADS Logic, which isn't a bad drawing program. I don't >> like hierachical schematics, so all of mine are flat, over 30 B-size >> pages some time. > >I like hiearchical schematics if you have a bunch of repeated "blocks" so that >you only have to make a change to, e.g., a component value once rather than 8 >times over. For just breaking down complexity, at some level hiearchy starts >to make sense, but whether or not the benefit outweighs the "everything right >here, all in front of you" appeal of a flat design pretty subjective... your >30 B pages undoubtedly works just peachy. I find 30 pages a bit much. The schematic for the main board in our widget is 10 'C' size pages, but it's viewable on 'C' size. If I were to redraw them they would probably go on 12 or 14 'B' sized pages. >> ftp://jjlarkin.lmi.net/22SS346A.pdf > >Nice! I don't get a lot of information out of that drawing. Certainly not as much as the top level of a hierarchical schematic.
From: krw on 5 Jan 2010 18:39 On Tue, 05 Jan 2010 10:52:53 -0800, Joerg <invalid(a)invalid.invalid> wrote: >John Larkin wrote: >> On Mon, 4 Jan 2010 20:22:14 -0800, "Joel Koltner" >> <zapwireDASHgroups(a)yahoo.com> wrote: >> >>> "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >>> news:hfa5k51hc8fad9u8b0dpqbae43p4lekho8(a)4ax.com... >>>> You haven't worked with The Brat. >>> I've never even worked with a layout woman. Heck, not even any female >>> hardware designers... although a few female programmers. (And one claimed to >>> have done digital hardware design at a PPOE...) >> >> >> The best two layout-ers I've worked with pre-Brat were women. >> > >Same here. The first one drove a souped-up Z28, Mario Andretti style. Never had a female layouter work on my designs. >> I've never worked with a full-time female circuit designer, or even >> met one to my knowledge. ... > > >I've worked with one that did switch-mode supply designs, something most >engineers seem not to enjoy at all. Note to readers: Too late, she's now >married. Um, does she still switch modes after she married? What does her husband think about that? ;-)
From: Joerg on 5 Jan 2010 20:34 krw wrote: > On Tue, 05 Jan 2010 10:52:53 -0800, Joerg <invalid(a)invalid.invalid> > wrote: > >> John Larkin wrote: >>> On Mon, 4 Jan 2010 20:22:14 -0800, "Joel Koltner" >>> <zapwireDASHgroups(a)yahoo.com> wrote: >>> >>>> "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >>>> news:hfa5k51hc8fad9u8b0dpqbae43p4lekho8(a)4ax.com... >>>>> You haven't worked with The Brat. >>>> I've never even worked with a layout woman. Heck, not even any female >>>> hardware designers... although a few female programmers. (And one claimed to >>>> have done digital hardware design at a PPOE...) >>> >>> The best two layout-ers I've worked with pre-Brat were women. >>> >> Same here. The first one drove a souped-up Z28, Mario Andretti style. > > Never had a female layouter work on my designs. > Some of my largest boards were done by female layouters. Three DIN connectors high extra length boards with eight or more layers and such. >>> I've never worked with a full-time female circuit designer, or even >>> met one to my knowledge. ... >> >> I've worked with one that did switch-mode supply designs, something most >> engineers seem not to enjoy at all. Note to readers: Too late, she's now >> married. > > Um, does she still switch modes after she married? What does her > husband think about that? ;-) Actually he is very skilled in the design of high power switch mode stuff so they are probably quite compatible :-) -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
From: Joerg on 5 Jan 2010 13:47
John Larkin wrote: > On Mon, 04 Jan 2010 20:31:49 -0600, krw <krw(a)att.bizzzzzzzzzzz> wrote: > >> On Mon, 4 Jan 2010 17:54:46 -0800, "Joel Koltner" >> <zapwireDASHgroups(a)yahoo.com> wrote: >> >>> "krw" <krw(a)att.bizzzzzzzzzzz> wrote in message >>> news:gj45k5tr1g3rqe72k3tbff33lnke7c5sdk(a)4ax.com... >>>> On Mon, 4 Jan 2010 15:02:59 -0800, "Joel Koltner" >>>> <zapwireDASHgroups(a)yahoo.com> wrote: >>>> That's the argument I get from the layout guy. >>> I know they exist (e.g., the guys at UltraCAD), but so far I've never worked >>> anywhere where the layout guy was particularly "proactive" in the sense of >>> suggesting interesting/potentially useful new ways to deal with parts >>> management... they instead seem to always have a reason why, no, you can't do >>> it the way you're suggesting (even though you've done so many times over >>> somewhere else...). C'est la vie... > > You haven't worked with The Brat. > Or my layouter for that matter. He always comes up with good ideas. >>> That's a bit more convenient, I just worry that I'll then forget it and that >>> somehow a DRC run won't catch it either. (We don't have a "formal checklist" >>> like John says he's working on to catch this sort of thing...) > > I'm not working on the checklist... The Brat is! > Still working off that Jeep that she bought with college "savings"? >> We don't have such a checklist either, but it's pretty hard to forget >> the power "gate" when it has 70 pins. ;-) OTOH, I can see it >> happening on an OpAmp, of thirty. >> >>>> I generally create the >>>> "gates" from the front of the schematic to the back and the power >>>> page(s) at the rear of the schematic. >>> That's how most of ours end up too. Things like multi-pin headers/connectors >>> usually end up on the first page if they contain signals that go "all over." > > The first page of our schematics is the block diagram and table of > contents. > That's what the guys at Cadsoft seem not to fully grasp :-( Otherwise Eagle would almost be perfect and their sales volume could more than double. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |