How do you design these days?
in [Design]
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From: Joel Koltner on 4 Jan 2010 23:22 "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message news:hfa5k51hc8fad9u8b0dpqbae43p4lekho8(a)4ax.com... > You haven't worked with The Brat. I've never even worked with a layout woman. Heck, not even any female hardware designers... although a few female programmers. (And one claimed to have done digital hardware design at a PPOE...) > I'm not working on the checklist... The Brat is! Would you be willing to post it when she's done for the benefit of the rest of us plebes? :-) Arguably we can possibly even add value, recounting our own foibles. > The first page of our schematics is the block diagram and table of > contents. Do you create those within PADS itself or use, e.g., Visio and then copy & paste? Do you use hierachical design on the schematic itself? We've had a half-hearted effort to keep a list of design revisions on the last page of the schematic, but it's just a table and a bunch of text boxes drawn in ORCAD itself, which makes it pretty much impossible to readily search or archive. It's better than nothing, though, so I can't really complain. ---Joel
From: krw on 4 Jan 2010 23:46 On Mon, 04 Jan 2010 20:21:08 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Mon, 04 Jan 2010 18:59:09 -0600, krw <krw(a)att.bizzzzzzzzzzz> wrote: > >>On Sun, 03 Jan 2010 22:33:34 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sun, 03 Jan 2010 19:43:46 -0600, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>> >>>>On Sun, 03 Jan 2010 16:49:45 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Sun, 03 Jan 2010 14:15:52 -0600, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>>>> >>>>>>On Sun, 03 Jan 2010 10:08:15 -0800, John Larkin >>>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>>> >>>>>>>On Fri, 01 Jan 2010 19:19:42 -0600, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>>>>>> >>>>>>>>On Fri, 01 Jan 2010 17:40:54 -0500, ehsjr <ehsjr(a)nospamverizon.net> >>>>>>>>wrote: >>>>>>>> >>>>>> >>>>>><snip> >>>>>> >>>>>>>>>You've got a steadier hand than I'll ever have. >>>>>>>>>I have to do it with a Dremel mounted in a drill press >>>>>>>>>adapter, and slide the board against guides clamped to >>>>>>>>>the bed. Even then ... :-( >>>>>>>> >>>>>>>>Sounds like you need a small milling machine. >>>>>>> >>>>>>>We had one of those PCB mills, on indefinite loan from a customer who >>>>>>>wasn't using it. It was such a hassle that we wound up not using it >>>>>>>too. >>>>>> >>>>>>Gotta be better than fence clamped to a drill press. >>>>>> >>>>>>>I can do the modest stuff with a knife and some kapton tape. After >>>>>>>that, it's easiest to just lay out a board and have a pcb house make a >>>>>>>few. >>>>>> >>>>>>You mean copper-clad kapton tape? >>>>> >>>>>No, just bits stuck to the copperclad and cut into patterns, as local >>>>>insulators. >>>> >>>>What good does that do? I guess I don't see the purpose of the >>>>insulator without a pad to solder to. Got a picture? >>> >>>Under the SO8... >>> >>>ftp://jjlarkin.lmi.net/BB_fast.JPG >> >>Neat. I would have thought you would have just hogged out the foil >>underneath. >> >>BTW, John, I've had some time to play with the fake caps and fake >>resistors. I looked up the pointer to your circuit in the archives >>but the pointee is gone. Any chance you could put it up again? Any >>other pointers would be very handy, too. I need something that's good >>for four quadrants (or at least bipolar currents). Thanks. > >I don't seem to have that around. I could redraw it, but it's not >adaptable to bipolar use so may not do you any good. Yeah, I need first and fourth quadrant, at least. My application is transformer coupled so I can bias the voltage anywhere but bipolar current is important. I think I have one that works, but it's not very pretty and takes a moose of an opamp. >We did do this... > >http://www.highlandtechnology.com/DSS/V420DS.html I remember that. >but the circuit is quite complex and it wouldn't be prudent to post it >publicly. That's fine. It's gotta be relatively cheap (cheaper than sixteen FET switches and port replicator). Thanks, anyway. >4 quadrants is even more interesting.
From: krw on 4 Jan 2010 23:50 On Mon, 04 Jan 2010 18:58:00 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Mon, 04 Jan 2010 20:31:49 -0600, krw <krw(a)att.bizzzzzzzzzzz> wrote: > >>On Mon, 4 Jan 2010 17:54:46 -0800, "Joel Koltner" >><zapwireDASHgroups(a)yahoo.com> wrote: >> >>>"krw" <krw(a)att.bizzzzzzzzzzz> wrote in message >>>news:gj45k5tr1g3rqe72k3tbff33lnke7c5sdk(a)4ax.com... >>>> On Mon, 4 Jan 2010 15:02:59 -0800, "Joel Koltner" >>>> <zapwireDASHgroups(a)yahoo.com> wrote: >>>> That's the argument I get from the layout guy. >>> >>>I know they exist (e.g., the guys at UltraCAD), but so far I've never worked >>>anywhere where the layout guy was particularly "proactive" in the sense of >>>suggesting interesting/potentially useful new ways to deal with parts >>>management... they instead seem to always have a reason why, no, you can't do >>>it the way you're suggesting (even though you've done so many times over >>>somewhere else...). C'est la vie... > >You haven't worked with The Brat. "The Brat" (TM) has a different motivation than most. >>>That's a bit more convenient, I just worry that I'll then forget it and that >>>somehow a DRC run won't catch it either. (We don't have a "formal checklist" >>>like John says he's working on to catch this sort of thing...) > >I'm not working on the checklist... The Brat is! That's what I need to get going. Our design reviews could sure use it. >>We don't have such a checklist either, but it's pretty hard to forget >>the power "gate" when it has 70 pins. ;-) OTOH, I can see it >>happening on an OpAmp, of thirty. >> >>>> I generally create the >>>> "gates" from the front of the schematic to the back and the power >>>> page(s) at the rear of the schematic. >>> >>>That's how most of ours end up too. Things like multi-pin headers/connectors >>>usually end up on the first page if they contain signals that go "all over." > >The first page of our schematics is the block diagram and table of >contents. I wanted to have the first page the top level hierarchy. That idea fell flat. We do have our change revisions on the first page (in WhoreCAD text boxes). We generally keep the revisions for the last two levels and whatever else fits. THe other engineer likes to conserve paper, for some reason.
From: John Larkin on 5 Jan 2010 00:09 On Mon, 4 Jan 2010 20:22:14 -0800, "Joel Koltner" <zapwireDASHgroups(a)yahoo.com> wrote: >"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >news:hfa5k51hc8fad9u8b0dpqbae43p4lekho8(a)4ax.com... >> You haven't worked with The Brat. > >I've never even worked with a layout woman. Heck, not even any female >hardware designers... although a few female programmers. (And one claimed to >have done digital hardware design at a PPOE...) The best two layout-ers I've worked with pre-Brat were women. I've never worked with a full-time female circuit designer, or even met one to my knowledge. I have worked with lots of female programmers, scientists, and managers. I know one physical chemist who got pregnant and didn't want to be around chemicals and magnets for the duration. She wandered the halls, saw some guys designing FPGAs, and decided to do that. So she did, very well. But she can do anything. She was the R&D manager last time I checked. > >> I'm not working on the checklist... The Brat is! > >Would you be willing to post it when she's done for the benefit of the rest of >us plebes? :-) Arguably we can possibly even add value, recounting our own >foibles. Sure, will do when it's presentable. Additions are welcome. > >> The first page of our schematics is the block diagram and table of >> contents. > >Do you create those within PADS itself or use, e.g., Visio and then copy & >paste? Do you use hierachical design on the schematic itself? We draw it with PADS Logic, which isn't a bad drawing program. I don't like hierachical schematics, so all of mine are flat, over 30 B-size pages some time. ftp://jjlarkin.lmi.net/22SS346A.pdf John
From: Joel Koltner on 5 Jan 2010 13:17
"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message news:2nh5k59u7thoqc6pvaassqbcrkvv0hcb34(a)4ax.com... > Sure, will do when it's presentable. Additions are welcome. Great, thanks John. > We draw it with PADS Logic, which isn't a bad drawing program. I don't > like hierachical schematics, so all of mine are flat, over 30 B-size > pages some time. I like hiearchical schematics if you have a bunch of repeated "blocks" so that you only have to make a change to, e.g., a component value once rather than 8 times over. For just breaking down complexity, at some level hiearchy starts to make sense, but whether or not the benefit outweighs the "everything right here, all in front of you" appeal of a flat design pretty subjective... your 30 B pages undoubtedly works just peachy. > ftp://jjlarkin.lmi.net/22SS346A.pdf Nice! ---Joel |