How to spec jitter for a digital NCO
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From: gretzteam on 31 May 2010 14:35 >> I understand that for arbitrary M and N, 'fout' will have the following >> shape: >> >> '6 6 6 6 7 6 6 6 6 7 6 6 6 6 7 etc...' (Here 6 and 7 being the number of >> input cycles). > >This makes sense if the NCO is some sort of a fractional N divider -- is >that what you're dealing with? > >Certainly that's not the behavior of a phase accumulating NCO. > Isn't this just an interpretation of what the bits do? The NCO is just a counter that increments by N every cycle with a modulo M. Say M=31 and N=5, the wrap-around rate in terms of input cycle would be: 6-6-6-6-7 6-6-6-6-7 6-6-6-6-7...which is on average 6.2cycles=31/5. So for fin=100MHz, fout= 100/6.2 = 16.1290322...MHz >Assuming that you mean timing jitter, and taking your sequence ('shape') >of the output signal, your ideal sequence would be >6.2 6.2 6.2 ...> >So your ideal minus your actual would go:> >0.2 0.4 0.6 0.8 0 0.2 0.4 ...> >If you take the average of this it'd go:> >-0.2 0.0 0.2 0.4 -0.4 -0.2 0.0 ... > > From this you can see immediately that your peak to peak jitter is 0.8 >(of whatever units you're using), and you can fairly easily calculate >your RMS jitter. Ok that helps me a lot! Thanks!
From: Eric Jacobsen on 31 May 2010 15:08 On 5/31/2010 11:21 AM, Jerry Avins wrote: > On 5/31/2010 2:11 PM, Eric Jacobsen wrote: >> On 5/31/2010 8:40 AM, gretzteam wrote: >>> Hi, >>> Say I have a simple x-bit NCO running at 'fin' (100MHz). M and N are >>> programmable. The output frequency of the NCO is given by: >>> fout = fin*(N/M) >>> >>> Assuming a perfect input clock, how can I specify the jitter of >>> 'fout'? I >>> understand there are different measure of jitter but can't really figure >>> out how they work with this system. >>> With 'nice' M and N, the NCO is performing an exact power of two divider >>> and the jitter should be 0 (again assuming the input clock is perfect). >>> >>> I understand that for arbitrary M and N, 'fout' will have the following >>> shape: >>> >>> '6 6 6 6 7 6 6 6 6 7 6 6 6 6 7 etc...' (Here 6 and 7 being the number of >>> input cycles). >>> >>> How is jitter specified for such a clock? >>> >>> Thanks! >> >> I've not actually heard of M and N being associated directly with an NCO >> before. Are you using an NCO or some sort of hybrid synthesizer? >> >> An NCO by itself, by definitions that I'm used to, will contain just the >> oscillator with a Phase Increment Register. I don't know why you'd need >> a divide-by-N when you can just reprogram the PIR for a lower frequency. > > Working the NCO at a frequency that allows a final division by a large > power of two is a dandy way to reduce jitter. Not very tunable, though. > > Jerry The OP's description of an NCO seems strange, though, and I'm trying to get clarification to better understand the issue. Usually fout is a function of the PIR contents and the update frequency only. I'm not sure how his description of N and M fit, especially since those terms are typical for synthesizers, not NCOs. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Tim Wescott on 31 May 2010 15:20 On 05/31/2010 11:35 AM, gretzteam wrote: >>> I understand that for arbitrary M and N, 'fout' will have the following >>> shape: >>> >>> '6 6 6 6 7 6 6 6 6 7 6 6 6 6 7 etc...' (Here 6 and 7 being the number > of >>> input cycles). >> >> This makes sense if the NCO is some sort of a fractional N divider -- is >> that what you're dealing with? >> >> Certainly that's not the behavior of a phase accumulating NCO. >> > > Isn't this just an interpretation of what the bits do? The NCO is just a > counter that increments by N every cycle with a modulo M. Say M=31 and N=5, > the wrap-around rate in terms of input cycle would be: > 6-6-6-6-7 6-6-6-6-7 6-6-6-6-7...which is on average 6.2cycles=31/5. Well, I don't know, because I don't know how you're defining your "NCO". The "normal" way is the way Eric Jacobsen said; there are other things that can serve as an "NCO" in a wider sense, but you have to specify. > > So for fin=100MHz, fout= 100/6.2 = 16.1290322...MHz > >> Assuming that you mean timing jitter, and taking your sequence ('shape') >> of the output signal, your ideal sequence would be >> 6.2 6.2 6.2 ...> >> So your ideal minus your actual would go:> >> 0.2 0.4 0.6 0.8 0 0.2 0.4 ...> >> If you take the average of this it'd go:> >> -0.2 0.0 0.2 0.4 -0.4 -0.2 0.0 ... >> >> From this you can see immediately that your peak to peak jitter is 0.8 >> (of whatever units you're using), and you can fairly easily calculate >> your RMS jitter. > > Ok that helps me a lot! Thanks! Particularly since I couldn't intuit your flavor of NCO from your description, don't take my example result as your real one! -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
From: dbd on 31 May 2010 15:25 On May 31, 8:40 am, "gretzteam" <gretzteam(a)n_o_s_p_a_m.yahoo.com> wrote: > Hi, > Say I have a simple x-bit NCO running at 'fin' (100MHz). M and N are > programmable. The output frequency of the NCO is given by: > fout = fin*(N/M) > ... > > How is jitter specified for such a clock? > > Thanks! Take a look at: http://www.designers-guide.org/Analysis/PLLjitter.pdf http://focus.ti.com/lit/an/swra029/swra029.pdf http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf Dale B. Dalrymple
From: Tim Wescott on 31 May 2010 15:26
On 05/31/2010 11:11 AM, Eric Jacobsen wrote: > On 5/31/2010 8:40 AM, gretzteam wrote: >> Hi, >> Say I have a simple x-bit NCO running at 'fin' (100MHz). M and N are >> programmable. The output frequency of the NCO is given by: >> fout = fin*(N/M) >> >> Assuming a perfect input clock, how can I specify the jitter of 'fout'? I >> understand there are different measure of jitter but can't really figure >> out how they work with this system. >> With 'nice' M and N, the NCO is performing an exact power of two divider >> and the jitter should be 0 (again assuming the input clock is perfect). >> >> I understand that for arbitrary M and N, 'fout' will have the following >> shape: >> >> '6 6 6 6 7 6 6 6 6 7 6 6 6 6 7 etc...' (Here 6 and 7 being the number of >> input cycles). >> >> How is jitter specified for such a clock? >> >> Thanks! > > I've not actually heard of M and N being associated directly with an NCO > before. Are you using an NCO or some sort of hybrid synthesizer? > > An NCO by itself, by definitions that I'm used to, will contain just the > oscillator with a Phase Increment Register. I don't know why you'd need > a divide-by-N when you can just reprogram the PIR for a lower frequency. > > Can you clarify? I would love to see the OP's definition of _his_ NCO. I have seen the term "NCO" to mean a lot of different things, though -- the one you describe is more or less the canonical one, although I've seen mention of using an IIR 'filter' with poles on the unit circle, I've seen mention of -- and used -- a simple divide-by-N, I've used a divide by in preceded by a sigma-delta modulator for higher frequency accuracy at the expense of some phase jitter, and there may be more out there that's passed before my eyes that I don't remember. Just like oscillators in analog electronics, there are a whole bunch of different ways to chop up a clock signal into another clock signal; it's well not to get stuck on any one thing. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com |