How to spec jitter for a digital NCO
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From: Steve Pope on 31 May 2010 23:04 gretzteam <gretzteam(a)n_o_s_p_a_m.yahoo.com> wrote: > Ok I've been thinking about this on the bus ride home. Those two approach cannot be the same. I fail to see where M plays a role in your setup. You only increment this modulo-M counter by 1, when the binary counter overflows (at the 2^NLSB boundary). The modulo-M counter doesn't give you >anything, in fact it is a simple binary counter. I'm assuming your M is my value "MOD" in my previous posts. With that, I'm not sure at all what you're saying. It's not a simple binary counter, it's modulo M where M might not be a power of two, thus it is a nonbinary counter. The frequencies your NCO might emit are different. If say M = 63, then the possible NCO frequencies would more closely spaced than if M = 64. > I understand you can make the LSB counter very long, with a lot of precision, but you're really only playing with N for a given # LSB. It seems like M is fixed to 2^NSLB. No, M can be a non power of 2. That's what I mean by a nonbinary counter with some different modulus. >In my setup, the overflow rate is fin*N/M. This is where I get some >'fractional' output frequencies. I use this to clock a binary counter and >get divided down version of this. You've lost me. >Am I getting this right? Give me a value of system clock, and desired output clock frequency and I will give you a numerical example. Steve
From: Eric Jacobsen on 1 Jun 2010 01:06 On 5/31/2010 1:37 PM, gretzteam wrote: >> Not incorrect -- just in need of clarification. >> >> The "DDS" style of NCO works well (and is by far what people usually >> mean when they say "NCO"), but gains a lot from the sine lookup -- this >> smooths out the inherent 'jagginess' from it's input clock, and >> essentially lets it interpolate zero crossing points in an analog system. >> >> When you just use the overflow then you have an unavoidable timing >> jitter that usually approaches +/- 1/2 an input clock peak-peak, with an >> RMS timing jitter that comes directly from the fact that the timing >> error is a sawtooth wave -- if you can stand this in your application, >> then you're home free. > > I see. I was expecting the peak-to-peak jitter would be 1 input clock peak > to peak. I don't think there is a way around this if I'm only willing to > use 'nice-synthesizable rising-edge only digital logic'. However, if the > input clock is fast relative to the generated clock, and the NCO has a good > resolution, the RMS jitter can be made quite low. Yes. It is not unusual to use the MSB of the phase accumulator as the output clock, as it'll be a nice, nearly 50% duty cycle. The output jitter will depend on things like the ratio of the output clock rate to input clock rate and the stability of the input clock. This is for a static phase increment value. If the NCO is controlled with a loop or something else, then the jitter will also depend on the characteristics of the control system. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Mark on 1 Jun 2010 08:44 On Jun 1, 1:06 am, Eric Jacobsen <eric.jacob...(a)ieee.org> wrote: > On 5/31/2010 1:37 PM, gretzteam wrote: > > > > > > >> Not incorrect -- just in need of clarification. > > >> The "DDS" style of NCO works well (and is by far what people usually > >> mean when they say "NCO"), but gains a lot from the sine lookup -- this > >> smooths out the inherent 'jagginess' from it's input clock, and > >> essentially lets it interpolate zero crossing points in an analog system. > > >> When you just use the overflow then you have an unavoidable timing > >> jitter that usually approaches +/- 1/2 an input clock peak-peak, with an > >> RMS timing jitter that comes directly from the fact that the timing > >> error is a sawtooth wave -- if you can stand this in your application, > >> then you're home free. > > > I see. I was expecting the peak-to-peak jitter would be 1 input clock peak > > to peak. I don't think there is a way around this if I'm only willing to > > use 'nice-synthesizable rising-edge only digital logic'. However, if the > > input clock is fast relative to the generated clock, and the NCO has a good > > resolution, the RMS jitter can be made quite low. > > Yes. It is not unusual to use the MSB of the phase accumulator as the > output clock, as it'll be a nice, nearly 50% duty cycle. The output > jitter will depend on things like the ratio of the output clock rate to > input clock rate and the stability of the input clock. > > This is for a static phase increment value. If the NCO is controlled > with a loop or something else, then the jitter will also depend on the > characteristics of the control system. > > -- > Eric Jacobsen > Minister of Algorithms > Abineau Communicationshttp://www.abineau.com- Hide quoted text - > > - Show quoted text - I think the OP's confusion is from a common misconception that many people have when starting to work with DDS's. The OP wants a square wave output. The usual DDS implementation uses a phase accumulator feeding a sine look up table feeding a DAC feeding a reconstruction filter to create a sine wave. The OP needs a square wave and is under the common misconception that one can simply leave off the look up table and DAC and filter and use the MSB to create the square wave. This method of course creates jitter and is the source of the confusion..... I think. To the OP, to minimize the jitter you have to retain the look up table DAC and reconstruction filter and then pass the sine wave through a comparator to get a square wave. It seems crazy I know... Think of it this way, the input DDS clock edges are in general asynchronous to the clock you want so the DDS clock edges are in effect "running through" the sine wave. The reconstruction filter smoothes these out. Then the comparator can create the true zero crossings. Without going through the analog sine wave steps, your output has no choice but to be coincident with the input clock edges. Mark
From: Eric Jacobsen on 1 Jun 2010 11:50 On 6/1/2010 5:44 AM, Mark wrote: > On Jun 1, 1:06 am, Eric Jacobsen<eric.jacob...(a)ieee.org> wrote: >> On 5/31/2010 1:37 PM, gretzteam wrote: >> >> >> >> >> >>>> Not incorrect -- just in need of clarification. >> >>>> The "DDS" style of NCO works well (and is by far what people usually >>>> mean when they say "NCO"), but gains a lot from the sine lookup -- this >>>> smooths out the inherent 'jagginess' from it's input clock, and >>>> essentially lets it interpolate zero crossing points in an analog system. >> >>>> When you just use the overflow then you have an unavoidable timing >>>> jitter that usually approaches +/- 1/2 an input clock peak-peak, with an >>>> RMS timing jitter that comes directly from the fact that the timing >>>> error is a sawtooth wave -- if you can stand this in your application, >>>> then you're home free. >> >>> I see. I was expecting the peak-to-peak jitter would be 1 input clock peak >>> to peak. I don't think there is a way around this if I'm only willing to >>> use 'nice-synthesizable rising-edge only digital logic'. However, if the >>> input clock is fast relative to the generated clock, and the NCO has a good >>> resolution, the RMS jitter can be made quite low. >> >> Yes. It is not unusual to use the MSB of the phase accumulator as the >> output clock, as it'll be a nice, nearly 50% duty cycle. The output >> jitter will depend on things like the ratio of the output clock rate to >> input clock rate and the stability of the input clock. >> >> This is for a static phase increment value. If the NCO is controlled >> with a loop or something else, then the jitter will also depend on the >> characteristics of the control system. >> >> -- >> Eric Jacobsen >> Minister of Algorithms >> Abineau Communicationshttp://www.abineau.com- Hide quoted text - >> >> - Show quoted text - > > I think the OP's confusion is from a common misconception that many > people have when starting to work with DDS's. > > The OP wants a square wave output. The usual DDS implementation uses > a phase accumulator feeding a sine look up table feeding a DAC > feeding a reconstruction filter to create a sine wave. > > The OP needs a square wave and is under the common misconception that > one can simply leave off the look up table and DAC and filter and use > the MSB to create the square wave. This method of course creates > jitter and is the source of the confusion..... I think. > > To the OP, to minimize the jitter you have to retain the look up table > DAC and reconstruction filter and then pass the sine wave through a > comparator to get a square wave. It seems crazy I know... > > Think of it this way, the input DDS clock edges are in general > asynchronous to the clock you want so the DDS clock edges are in > effect "running through" the sine wave. The reconstruction filter > smoothes these out. Then the comparator can create the true zero > crossings. Without going through the analog sine wave steps, your > output has no choice but to be coincident with the input clock edges. > > Mark FWIW, I concur that if you really want to minimize jitter in a DDS/NCO generated clock signal, this is a good way to do it. It may not be all that useful if the target platform is all-digital and running off the same system clock, though. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Vladimir Vassilevsky on 1 Jun 2010 12:01
Mark wrote: > The OP needs a square wave and is under the common misconception that > one can simply leave off the look up table and DAC and filter and use > the MSB to create the square wave. This method of course creates > jitter and is the source of the confusion..... I think. > > To the OP, to minimize the jitter you have to retain the look up table > DAC and reconstruction filter and then pass the sine wave through a > comparator to get a square wave. Yes-yes-yes. However, if the problem is limited to digital <-> digital solution and there is no way to oversample, one can round the phase to the neareast MSB instead of truncation, and then do noise shaping to shift the jitter spectrum out of the band of interest. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com |