How to spec jitter for a digital NCO
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From: dbd on 1 Jun 2010 13:30 On Jun 1, 9:30 am, Eric Jacobsen <eric.jacob...(a)ieee.org> wrote: >... > ADI and Qualcomm used to have some really good app-notes online about > jitter/noise reduction in NCO/DDS outputs. There are some simple > techniques that have pretty good bang for the buck. > Eric Jacobsen Still do. AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter http://www.analog.com/static/imported-files/application_notes/5847948184484445938457260443675626756108420567021238941550065879349464383423509029308534504114752208671024345AN_756_0.pdf AN-823: Direct Digital Synthesizers in Clocking Applications Time http://www.analog.com/static/imported-files/application_notes/475354741144165304775709740692131461831AN823_0.pdf Section 7 of: http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf "DDS as a Clock Generator" Jitter reduction techniques from TI and Designer's Guide are in my earliest post. Dale B. Dalrymple
From: Eric Jacobsen on 1 Jun 2010 13:52 On 6/1/2010 10:12 AM, Steve Pope wrote: > Eric Jacobsen<eric.jacobsen(a)ieee.org> wrote: > >> On 6/1/2010 9:53 AM, Steve Pope wrote: > >>> Eric Jacobsen<eric.jacobsen(a)ieee.org> wrote: > >>>> Yes. It is not unusual to use the MSB of the phase accumulator as the >>>> output clock, as it'll be a nice, nearly 50% duty cycle. The output >>>> jitter will depend on things like the ratio of the output clock rate to >>>> input clock rate and the stability of the input clock. > >>> It seems clear to me that, unless the output clock is a submultiple >>> of the input clock, this leads to intrinsic jitter. That is, >>> upon different 0 -> 1 transitions of the MSB you will have different >>> values in the LSB's, meaning you are at a slightly different >>> time pointin the oscillator period. > >>> This constrasts with a conventional NCO which uses a sinusoid >>> function formed using the entire phase counter as its input >>> (or at least, many MS bits of it); then you do not have this >>> particular source of intrinsic jitter... assuming your sinusoid is >>> eventually filtered. > >> It winds up being exactly the same thing, and it's not hard to explain >> why: If the phase accumulator output is the address to the sine LUT, >> then the MSB selects the polarity, or which half, of the sine output. >> So the phase accumulator MSB maps directly to the sign bit of the output >> sine wave. This means there's really no difference in output jitter >> between the accumulator MSB and the sine wave in the digital domain. >> That little bit of jitter gets filtered out really easily if there is >> post-filtering, but if it all stays in the digital domain then using the >> MSB (if one wants a 50% clock) or the rollover pulse (aka the carry-out >> of the accumulator) works just as well. > > I think I see what you're saying, which is if a digital clock has > jitter, then nobody cares so long as the result of the subsequent > digital processing is bit-exact with what it would have been > with a jitter-free clock. > > Therefore, jitter only really applies to clocks used for an analog > purpose, such as an ADC sample clock. It is in this scenario that > you will need to filter to remove any intrinsic jitter, and it > is also in this scenario where you would like to have your NCO > emit something that is a "filterable" as possible. I feel the > sinusoid generator meets this criterion a little better. > >>> Now, I have a freshman question... what exactly is a "DDS"? I know >>> what an NCO is. :-) > >> Direct Digital Synthesis or Direct Digital Synthesizer > >> As far as I've ever been able to tell it is completely synonymous with >> NCO. DDS gets used a lot in comm literature, though, especially data >> sheets or product descriptions. > > I just did some googling, and DDS seems to describe a system comprising > a clock source, NCO, DAC, and reconstruction filter. > > Steve Except that tons of product literature over the years have shown NCOs completely contained within a digital system as a DDS, and Qualcomm (and ADI) have historically sold standalone NCOs labelled as a "DDS". In ADI's case they often integrate the DAC. Like many things in this industry, these nomenclatures aren't held to strict discipline. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Mark K on 1 Jun 2010 15:56 > It winds up being exactly the same thing, and it's not hard to explain > why: If the phase accumulator output is the address to the sine LUT, > then the MSB selects the polarity, or which half, of the sine output. > So the phase accumulator MSB maps directly to the sign bit of the output > sine wave. This means there's really no difference in output jitter >between the accumulator MSB and the sine wave in the digital domain. but if do go into the anlog domain, the Zero crossing after the reconstruction filter does not happen at the exact same time as the sign bit flip at the DAC output. Next I think it depends on what you mean by "the digital domain". (Reminds me of Bill Clinton) In a synchronous digital system edges can only happen synchronized with the input clock. Therefore any square wave will in general have +/- 1 clock jitter. But if by digital domain you mean DSP, then you can still REPRESENT a sine wave in the digital domain without jitter as a series of numbers. Even though the sample points will roll through your sine wave, the series of numbers can be made to be correct to represent a jitter free sine. These of course are simply the numbers that comne out of the look up table that you would feed into the DAC if you were going to the anlog domain. Mark
From: Rob Gaddi on 1 Jun 2010 16:23 On 6/1/2010 9:24 AM, Rob Gaddi wrote: > On 5/31/2010 1:37 PM, gretzteam wrote: >>> Not incorrect -- just in need of clarification. >>> >>> The "DDS" style of NCO works well (and is by far what people usually >>> mean when they say "NCO"), but gains a lot from the sine lookup -- this >>> smooths out the inherent 'jagginess' from it's input clock, and >>> essentially lets it interpolate zero crossing points in an analog >>> system. >>> >>> When you just use the overflow then you have an unavoidable timing >>> jitter that usually approaches +/- 1/2 an input clock peak-peak, with an >>> RMS timing jitter that comes directly from the fact that the timing >>> error is a sawtooth wave -- if you can stand this in your application, >>> then you're home free. >> >> I see. I was expecting the peak-to-peak jitter would be 1 input clock >> peak >> to peak. I don't think there is a way around this if I'm only willing to >> use 'nice-synthesizable rising-edge only digital logic'. However, if the >> input clock is fast relative to the generated clock, and the NCO has a >> good >> resolution, the RMS jitter can be made quite low. >> >> > > Exactly right. You're calling the PTP jitter 1 clock, you're hearing +/- > 1/2 clock, same thing. It sounds like you've got some downstream logic > that you want to trigger periodically. And you're planning to use the > overflow from the phase accumulator as a single input clock wide pulse > to trigger that logic, all of which is on the same input clock. > > Yep that works, yep it jitters, yep if you can push the clock frequency > high enough you can often manage to not care about the jitter. If that's > not feasible you'll need to go to extreme measures, either an external > PLL with an analog VCO or a sine wave DDS -> DAC -> filter -> comparator > -> new clock input. Either of these techniques will mean that your new > clock is on a clock domain that will have to be treated entirely > asynchronously. The data handoff problems that creates are a real pain, > but not insurmountable so long as you're willing to pay serious > attention at each handoff. > One more note. If you are trying to do what I described above, then depending on what frequencies you need to generate there is a zero-jitter way of doing it. Instead of using an NCO and triggering off of the carry out, you just use a modulo-N counter. Personally I tend to use downcounters so that the borrow out = the reload signal = the trigger out, but I think that's more an article of religious faith than anything that matters to the implementation. For an N of the same length this changes the frequencies you're able to synthesize. With DDS the frequencies are evenly spaced. A divide-by-N counter spaces them hyperbolically; the choices for frequency become, every clock, every other, every third, etc, which means that you've got more resolution at lower frequencies but way less at frequencies near the clock rate. Still, this allows you to hit on the head frequencies that you can't get to exactly via an NCO, and does so with zero jitter. -- Rob Gaddi, Highland Technology Email address is currently out of order
From: gretzteam on 2 Jun 2010 19:23
>> >> Exactly right. You're calling the PTP jitter 1 clock, you're hearing +/- >> 1/2 clock, same thing. It sounds like you've got some downstream logic >> that you want to trigger periodically. And you're planning to use the >> overflow from the phase accumulator as a single input clock wide pulse >> to trigger that logic, all of which is on the same input clock. >> >> Yep that works, yep it jitters, yep if you can push the clock frequency >> high enough you can often manage to not care about the jitter. If that's >> not feasible you'll need to go to extreme measures, either an external >> PLL with an analog VCO or a sine wave DDS -> DAC -> filter -> comparator >> -> new clock input. Either of these techniques will mean that your new >> clock is on a clock domain that will have to be treated entirely >> asynchronously. The data handoff problems that creates are a real pain, >> but not insurmountable so long as you're willing to pay serious >> attention at each handoff. >> > >One more note. If you are trying to do what I described above, then >depending on what frequencies you need to generate there is a >zero-jitter way of doing it. Instead of using an NCO and triggering off >of the carry out, you just use a modulo-N counter. Personally I tend to >use downcounters so that the borrow out = the reload signal = the >trigger out, but I think that's more an article of religious faith than >anything that matters to the implementation. > >For an N of the same length this changes the frequencies you're able to >synthesize. With DDS the frequencies are evenly spaced. A divide-by-N >counter spaces them hyperbolically; the choices for frequency become, >every clock, every other, every third, etc, which means that you've got >more resolution at lower frequencies but way less at frequencies near >the clock rate. Still, this allows you to hit on the head frequencies >that you can't get to exactly via an NCO, and does so with zero jitter. > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order Hi, Thanks for all the answers! That leaves me a lot to think about. I should have said that this is for a purely digital application. I'm not trying to generate a sine wave, and don't have a LUT, won't go through analog back and forth etc... I was just trying to calculate how much jitter I get for a given NCO depending on M, N and the input clock. Say we have a 200MHz clock and want to generate a 32MHz clock. The ratio is 6.25. We could set an NCO with N=4 and M=25. What I mean by this is a modulo-25 counter that increments by 4 every cycle. The overflow rate would be 32MHz. The sequence in terms of input clock cycle goes like: 7 6 6 6 7 6 6 6 7 6 6 6 The ideal sequence would have been: 6.25 6.25 6.25 6.25 And we can calculate the timing jitter (peak-peak or RMS) from this. Now if we divide this 32MHz by two, the sequence becomes 13 12 13 12 13 12...we could calculate the jitter again. Then if we divide by two again, the sequence becomes 25 25 25 25...jitter is gone! So basically, if the original 'period' of the NCO sequence is a power of 2, there is a divide ratio that would yield a jitter free clock. This was not obvious to me. Still struggling to find an analytical solution for the jitter given M and N. Not sure this is possible without actually calculating the period. Diego |