How to spec jitter for a digital NCO
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From: Rob Gaddi on 1 Jun 2010 12:24 On 5/31/2010 1:37 PM, gretzteam wrote: >> Not incorrect -- just in need of clarification. >> >> The "DDS" style of NCO works well (and is by far what people usually >> mean when they say "NCO"), but gains a lot from the sine lookup -- this >> smooths out the inherent 'jagginess' from it's input clock, and >> essentially lets it interpolate zero crossing points in an analog system. >> >> When you just use the overflow then you have an unavoidable timing >> jitter that usually approaches +/- 1/2 an input clock peak-peak, with an >> RMS timing jitter that comes directly from the fact that the timing >> error is a sawtooth wave -- if you can stand this in your application, >> then you're home free. > > I see. I was expecting the peak-to-peak jitter would be 1 input clock peak > to peak. I don't think there is a way around this if I'm only willing to > use 'nice-synthesizable rising-edge only digital logic'. However, if the > input clock is fast relative to the generated clock, and the NCO has a good > resolution, the RMS jitter can be made quite low. > > Exactly right. You're calling the PTP jitter 1 clock, you're hearing +/- 1/2 clock, same thing. It sounds like you've got some downstream logic that you want to trigger periodically. And you're planning to use the overflow from the phase accumulator as a single input clock wide pulse to trigger that logic, all of which is on the same input clock. Yep that works, yep it jitters, yep if you can push the clock frequency high enough you can often manage to not care about the jitter. If that's not feasible you'll need to go to extreme measures, either an external PLL with an analog VCO or a sine wave DDS -> DAC -> filter -> comparator -> new clock input. Either of these techniques will mean that your new clock is on a clock domain that will have to be treated entirely asynchronously. The data handoff problems that creates are a real pain, but not insurmountable so long as you're willing to pay serious attention at each handoff. -- Rob Gaddi, Highland Technology Email address is currently out of order
From: Eric Jacobsen on 1 Jun 2010 12:30 On 6/1/2010 9:01 AM, Vladimir Vassilevsky wrote: > > > Mark wrote: > >> The OP needs a square wave and is under the common misconception that >> one can simply leave off the look up table and DAC and filter and use >> the MSB to create the square wave. This method of course creates >> jitter and is the source of the confusion..... I think. >> >> To the OP, to minimize the jitter you have to retain the look up table >> DAC and reconstruction filter and then pass the sine wave through a >> comparator to get a square wave. > > Yes-yes-yes. However, if the problem is limited to digital <-> digital > solution and there is no way to oversample, one can round the phase to > the neareast MSB instead of truncation, and then do noise shaping to > shift the jitter spectrum out of the band of interest. > > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultant > http://www.abvolt.com ADI and Qualcomm used to have some really good app-notes online about jitter/noise reduction in NCO/DDS outputs. There are some simple techniques that have pretty good bang for the buck. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Steve Pope on 1 Jun 2010 12:53 Eric Jacobsen <eric.jacobsen(a)ieee.org> wrote: >Yes. It is not unusual to use the MSB of the phase accumulator as the >output clock, as it'll be a nice, nearly 50% duty cycle. The output >jitter will depend on things like the ratio of the output clock rate to >input clock rate and the stability of the input clock. It seems clear to me that, unless the output clock is a submultiple of the input clock, this leads to intrinsic jitter. That is, upon different 0 -> 1 transitions of the MSB you will have different values in the LSB's, meaning you are at a slightly different time pointin the oscillator period. This constrasts with a conventional NCO which uses a sinusoid function formed using the entire phase counter as its input (or at least, many MS bits of it); then you do not have this particular source of intrinsic jitter... assuming your sinusoid is eventually filtered. Now, I have a freshman question... what exactly is a "DDS"? I know what an NCO is. :-) Steve
From: Eric Jacobsen on 1 Jun 2010 13:00 On 6/1/2010 9:53 AM, Steve Pope wrote: > Eric Jacobsen<eric.jacobsen(a)ieee.org> wrote: > >> Yes. It is not unusual to use the MSB of the phase accumulator as the >> output clock, as it'll be a nice, nearly 50% duty cycle. The output >> jitter will depend on things like the ratio of the output clock rate to >> input clock rate and the stability of the input clock. > > It seems clear to me that, unless the output clock is a submultiple > of the input clock, this leads to intrinsic jitter. That is, > upon different 0 -> 1 transitions of the MSB you will have different > values in the LSB's, meaning you are at a slightly different > time pointin the oscillator period. > > This constrasts with a conventional NCO which uses a sinusoid > function formed using the entire phase counter as its input > (or at least, many MS bits of it); then you do not have this > particular source of intrinsic jitter... assuming your sinusoid is > eventually filtered. It winds up being exactly the same thing, and it's not hard to explain why: If the phase accumulator output is the address to the sine LUT, then the MSB selects the polarity, or which half, of the sine output. So the phase accumulator MSB maps directly to the sign bit of the output sine wave. This means there's really no difference in output jitter between the accumulator MSB and the sine wave in the digital domain. That little bit of jitter gets filtered out really easily if there is post-filtering, but if it all stays in the digital domain then using the MSB (if one wants a 50% clock) or the rollover pulse (aka the carry-out of the accumulator) works just as well. > Now, I have a freshman question... what exactly is a "DDS"? I know > what an NCO is. :-) Direct Digital Synthesis or Direct Digital Synthesizer As far as I've ever been able to tell it is completely synonymous with NCO. DDS gets used a lot in comm literature, though, especially data sheets or product descriptions. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Steve Pope on 1 Jun 2010 13:12
Eric Jacobsen <eric.jacobsen(a)ieee.org> wrote: >On 6/1/2010 9:53 AM, Steve Pope wrote: >> Eric Jacobsen<eric.jacobsen(a)ieee.org> wrote: >>> Yes. It is not unusual to use the MSB of the phase accumulator as the >>> output clock, as it'll be a nice, nearly 50% duty cycle. The output >>> jitter will depend on things like the ratio of the output clock rate to >>> input clock rate and the stability of the input clock. >> It seems clear to me that, unless the output clock is a submultiple >> of the input clock, this leads to intrinsic jitter. That is, >> upon different 0 -> 1 transitions of the MSB you will have different >> values in the LSB's, meaning you are at a slightly different >> time pointin the oscillator period. >> This constrasts with a conventional NCO which uses a sinusoid >> function formed using the entire phase counter as its input >> (or at least, many MS bits of it); then you do not have this >> particular source of intrinsic jitter... assuming your sinusoid is >> eventually filtered. >It winds up being exactly the same thing, and it's not hard to explain >why: If the phase accumulator output is the address to the sine LUT, >then the MSB selects the polarity, or which half, of the sine output. >So the phase accumulator MSB maps directly to the sign bit of the output >sine wave. This means there's really no difference in output jitter >between the accumulator MSB and the sine wave in the digital domain. >That little bit of jitter gets filtered out really easily if there is >post-filtering, but if it all stays in the digital domain then using the >MSB (if one wants a 50% clock) or the rollover pulse (aka the carry-out >of the accumulator) works just as well. I think I see what you're saying, which is if a digital clock has jitter, then nobody cares so long as the result of the subsequent digital processing is bit-exact with what it would have been with a jitter-free clock. Therefore, jitter only really applies to clocks used for an analog purpose, such as an ADC sample clock. It is in this scenario that you will need to filter to remove any intrinsic jitter, and it is also in this scenario where you would like to have your NCO emit something that is a "filterable" as possible. I feel the sinusoid generator meets this criterion a little better. >> Now, I have a freshman question... what exactly is a "DDS"? I know >> what an NCO is. :-) >Direct Digital Synthesis or Direct Digital Synthesizer >As far as I've ever been able to tell it is completely synonymous with >NCO. DDS gets used a lot in comm literature, though, especially data >sheets or product descriptions. I just did some googling, and DDS seems to describe a system comprising a clock source, NCO, DAC, and reconstruction filter. Steve |