How to spec jitter for a digital NCO
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From: gretzteam on 31 May 2010 18:16 >Nothing wrong with running a sim if an analytical expression does >not come immediately to mind. > >Back to the modulo arithmetic. > >Fc = system clock >MOD = modulo of the MSB's of the phase counter >NLSB = number of LSB bits (counting in binary) in the phase counter > to the right of the above MSB's > >Your NCO can then generate any frequency which is a multiple of > > Fc / (MOD * 2^NLSB) > >without any intrinsic jitter. If that is good enough for your >application then do it, and save yourself the trouble of calculating >the jitter in a suboptimal design. > >Steve Hi, I don't quite understand what MOD and NLSB stands for. Maybe I'm just too much into my own design and need to take a step back! Are you saying you have a B-bit counter with Modulo M. Every time it overflows, you increment another counter with NLSB-bit?
From: Steve Pope on 31 May 2010 18:36 gretzteam <gretzteam(a)n_o_s_p_a_m.yahoo.com> replies to my post, >>Back to the modulo arithmetic. >> >>Fc = system clock >>MOD = modulo of the MSB's of the phase counter >>NLSB = number of LSB bits (counting in binary) in the phase counter >> to the right of the above MSB's >> >>Your NCO can then generate any frequency which is a multiple of >> >> Fc / (MOD * 2^NLSB) >> >>without any intrinsic jitter. > I don't quite understand what MOD and NLSB stands for. Maybe I'm > just too much into my own design and need to take a step back! Consider a phase counter whose bits are split into least-significant and most-significant sections. The LS section is NLSB bits and counts modulo 2^NLSB. The MS section is ceil(log2(MOD)) bits and counts modulo MOD. The entire counter is modulo MOD * 2^NLSB. At system clock rate Fs, this counter increments by an integer number of LSB's, and will generate the above frequencies without intrinsic jitter. There may be jitter from how your NCO output is smoothed, etc., but the phase counter itself is exact. If your goal is to generate any of a number of evenly-spaced NCO frequencies, this is how you want to do it unless there is some really stunning reason to do it otherwise. Steve
From: gretzteam on 31 May 2010 19:43 >>>Back to the modulo arithmetic. >>> >>>Fc = system clock >>>MOD = modulo of the MSB's of the phase counter >>>NLSB = number of LSB bits (counting in binary) in the phase counter >>> to the right of the above MSB's >>> >>>Your NCO can then generate any frequency which is a multiple of >>> >>> Fc / (MOD * 2^NLSB) >>> >>>without any intrinsic jitter. > >> I don't quite understand what MOD and NLSB stands for. Maybe I'm >> just too much into my own design and need to take a step back! > >Consider a phase counter whose bits are split into least-significant >and most-significant sections. > >The LS section is NLSB bits and counts modulo 2^NLSB. The MS section >is ceil(log2(MOD)) bits and counts modulo MOD. The entire counter >is modulo MOD * 2^NLSB. At system clock rate Fs, this counter >increments by an integer number of LSB's, and will generate the >above frequencies without intrinsic jitter. > >There may be jitter from how your NCO output is smoothed, etc., >but the phase counter itself is exact. > >If your goal is to generate any of a number of evenly-spaced >NCO frequencies, this is how you want to do it unless there is some >really stunning reason to do it otherwise. >Steve Interesting, this is actually completely backward from what I was doing! You increment by N the part of the counter that wraps around at the natural 2^NLSB boundary. When this wraps around, you increment by '1' a modulo-M counter. Right? I wonder how different this is from having the modulo-M counter increment by N, and use the overflow to clock a normal counter with NLSB bits. Diego
From: Steve Pope on 31 May 2010 21:26 gretzteam <gretzteam(a)n_o_s_p_a_m.yahoo.com> replies to my post, >>>>Back to the modulo arithmetic. [snip] > Interesting, this is actually completely backward from what > I was doing! You increment by N the part of the counter that > wraps around at the natural 2^NLSB boundary. When this wraps > around, you increment by '1' a modulo-M counter. Right? Yep > I wonder how different this is from having the modulo-M counter > increment by N, and use the overflow to clock a normal counter > with NLSB bits. Well, the total (LS bits plus MS bits) is the same modulus either way. There are only two differences that I can see: (1) When interpreting the counter value to drive the logic/LUT creating your sinusoid, the interpreation will be different. (2) In my approach, if you want to increase the frequency resolution you just add more LSB's to the binary counter. You would have to increase the modulo counter modulus, or add a third stage of counter on its LS side. Neither of these seem like they would cause you much trouble. [Tangentially, there are no "abnormal" counters. In the above, you mean a "binary" counter.] Steve
From: gretzteam on 31 May 2010 22:37
>gretzteam <gretzteam(a)n_o_s_p_a_m.yahoo.com> replies to my post, > >>>>>Back to the modulo arithmetic. > >[snip] > >> Interesting, this is actually completely backward from what >> I was doing! You increment by N the part of the counter that >> wraps around at the natural 2^NLSB boundary. When this wraps >> around, you increment by '1' a modulo-M counter. Right? > >Yep Ok I've been thinking about this on the bus ride home. Those two approach cannot be the same. I fail to see where M plays a role in your setup. You only increment this modulo-M counter by 1, when the binary counter overflows (at the 2^NLSB boundary). The modulo-M counter doesn't give you anything, in fact it is a simple binary counter. I understand you can make the LSB counter very long, with a lot of precision, but you're really only playing with N for a given # LSB. It seems like M is fixed to 2^NSLB. In my setup, the overflow rate is fin*N/M. This is where I get some 'fractional' output frequencies. I use this to clock a binary counter and get divided down version of this. Am I getting this right? Diego |