Schematic preferences
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From: krw on 18 Jan 2010 20:17 On Mon, 18 Jan 2010 13:37:16 -0700, D Yuniskis <not.going.to.be(a)seen.com> wrote: >Hi, > >Of course, this is *highly* subjective -- but, I'd enjoy hearing >folks' "conventions" used when preparing schematics (that *others* >will consume -- how you scribble for your own purposes isn't >important as it depends a lot on what *you* want out of the >drawing). I really want the same thing out of the schematic as do my "customers". In a year I won't remember what I did, so it's got to be readable (source code is the same deal - in spades). >I try to follow some general rules -- but also feel free to bend >them as needed. Most have evolved over the years from different >employers, standards, experience, etc. > >E.g., I *tend* to prefer landscape orientation -- though I >drew a B size "portrait" this morning in lieu of a C size >landscape. Yes, Landscape always seems to work out better. I just use 11x17 and stick it in a notebook sideways, with a fold. I'd do longer (I really print with a 1" offset so it comes out 11"x18") but haven't found I need more space that direction (without running out of vertical space first). OTOH, the other engineer likes C-size prints. I find they're a PITA on the bench (or pretty much anywhere). I end up printing his on 11x17 and squinting. ;-) >I try to include a block diagram of any "sizable" design early >in the document. I try to draft the individual pages so that >they roughly correspond with the blocks in that diagram. I try, though the drawing tools suck. I'd much prefer a hierarchical design, killing both birds, but the software isn't up to it. >I prefer spreading things over one sheet instead of trying to cram >everything onto one sheet -- unless the design is small enough >to do so without making that sheet cluttered. I.e., it is easier >to trace a signal on a single sheet than to have to flip to >another sheet; but, if there is a ratsnest of signals on that >one sheet, then tracing the signal can be perilous. I can usually keep off-sheet connectors to a minimum, placing an entire "channel" or such one sheet - maybe two. There is usually a logical break somewhere. It often costs a bit of paper, though. >Smallest page size to realistically support the design subject >to the remainder of these criteria. E.g., sure, you can fit >everything on an E-size drawing, but reproducing that drawing >(either full size or in "published" documentation) and *using* >that drawing become a real PITA! Sooner or later the design is going to overflow a sheet. Not only is "E-size" a PITA, but so is "C-Size", IMO. Larger pages have more signals running around, too. Long wires are hard to follow. >[I vacillate between preferring B or C size drawings. C is nice >in that it reduces to A nicely (i.e., with the same aspect ratio) >OTOH, B is nice because reducing to A leaves room along the >binding edge -- which must be located "above" the drawing! -- for >three hole punch *or* more professional binding. And, B size >can always be reproduced full size with "fold outs". (frown) B >size (reduced or otherwise) is currently en vogue -- perhaps a >consequence of my aging eyes? :> ] Get glasses. ;-) Bifocal reading glasses (two strengths, both for close work) work for me. >Aside from "general power", all signals that span pages *must* >come to the edge of the page. I don't like hunting for signals >in the middle of a page even if there is a grid reference to help >me locate it. It's just easier to conceptualize: "OK, this is >used elsewhere" or "This comes from someplace else" so I >know when something I am interested in involves other sheets. I agree, though I'd rather have signals connected on a page by name (as long as it's *clear*) than connectors broken apart and scattered all over the schematic. Sometimes it's not clear what the best solution is. >One signal, one name. One *instance* of that name per sheet! >Signals spanning pages are named at the edge of the page. Good idea, when it's possible without making the sheet look like a rat's nest. It usually is, though there are exceptions. >For designs of "suitable complexity" (in terms of sheets/signals), >I tag off page references with locations of the other "end(s)" >of the signal. If its a small design -- or, if the schematic is >broken down intuitively -- I assume the "other ends" will be >self explanatory. *ALWAYS* include off-sheet references. >"Left to right, top to bottom" Left to right (bidirectionals go either way unless there is tristate output on the net - then it gets more complicated). Top and bottom are for power only. >Eschew buses -- except on "block diagrams". Show individual >signals. Avoid unnecessary "bends" in signals. *Most* signals >parallel to page edges (some tools prevent you from doing otherwise). Wrong! Busses wherever they make sense. *NEVER* connect bussed signals off page. Off-page connectors on busses are shown as busses *only*. They get fanned out to nets on the page, as close to the part as possible. Do you really draw 64 individual wires with 64 off-page connectors for each wire in a 64-bit data bus? Ick! >Symbols oriented horizontally and suggestive of the direction >of signal flow (i.e., a gate in a feedback path can point to the >left). "Rocket ships crash (and burn)" :> Agreed. >Exploit symmetry and repetition. Step and repeat is your friend. Hierarchy is your friend. Schematic entry tools aren't. ;-) Be careful with step and repeat. It's *really* easy to forget to change all instances of facilities that differ between copies. DRC and browsing the netlist can help here. >As with *anything*, color has no significance! Significance, no, but importance, yes. IOW, the netlister shouldn't care about color but the human reading it does. It *must* be consistent. >Avoid 4-way streets -- unless their use significantly cleans >up the appearance. "Dots" (big ones!) on all connections >(mandated by the relaxed 4WS rule). I don't have problems with 4-way streets. Dots are plain enough to see. >Descriptive symbols (e.g., a diode bridge looks like a diamond) >and informative symbols (e.g., IEEE unless the device *really* >is a "black box" -- I don't consider *memory* to be a black box!) IEEE symbols suck. Rockets and bullets, everything else is a box; clocks and active levels marked appropriately >DeMorgan equivalents as appropriate. (I won't get into the rules >I use for building symbols as they get pretty involved) Yes, and signal names must match the symbol's polarity. >Reference designator before device name/value. Either both to >one side (left/right/top/bottom) or one on each side (left/right, >top/bottom). I put the RefID on top of the value with the value inside the component if it fits. >Unless a connector(s) inherently *merits* location on a separate >sheet (e.g., a PCI connector whose "pins" feed many other sheets), >locate the connector with the signals that tie to it (i.e., no >sheets full of connectors). That depends. Sometimes a connector sheet can be used to show the layout of the connectors. This is very handy when there are a lot of the same kinds of connectors. Again, the idea is to convey as much information as possible about the board. >Don't tie the schematic to a physical implementation. I.e., >the symbol for a connector shouldn't physically look like >the connector just as the symbol for a transistor doesn't >look like the transistor itself! If you need to clarify >the appearance or pin layout of a component, do so in >text or other documentation outside of the "schematic" itself. Diagree. It's very handy to have our XLR connectors look like XLR connectors, in the proper orientation. Information. Interboard connectors and headers also are drawn physically (in order, odds on one side and evens on the other). BNCs are drawn big-circle little circle/dot (dots=male, circles=female). >Decoupling caps specifically required by individual components >located proximal to the component symbols themselves. Other >"general" bypass caps grouped on a single sheet. Power and >ground connections not explicitly shown on components tabulated >on that same sheet, if possible. If possible. Large components get their own power/ground/decoupling (sometimes clocks or references) sheets. Small components (gates, op-amps, etc.) get power on the pages they appear. I'd change that if I were king, but the software sucks. >Only *terse* notes re: layout/manufacture/test on the actual >drawings; anything more verbose goes on a "notes" sheet. We put ECO notes on the sheets in red before the ECO and in blue for one revision after, in addition to the "Notes:" block on page-1. We also put a note on each subcircuit explaining what it is: +--------------------+ +-------------------------------+ | 4-pole Butterworth | - or - | Load Switching Bus | | H.P. F0=1kHz G=6dB | +---+---+---+---+---+---+---+---+ +--------------------+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +---+---+---+---+---+---+---+---+ |8nF|4nF|2nF|1nF|800|400|200|100| +---+---+---+---+---+---+---+---+ >On analog portions of the design, test voltage annotations >and 'scope traces, where *essential*. Remember, everything you >put on the drawing has to be *maintained*! If you make a change, >are you prepared to capture another 'scope trace? :> No pictures. They take way too much space. Voltages, yes. Keping any documentation up to date is a problem. Notes are no different than comments in code. >Document history on the cover page *only*. One firm I worked for >used to summarize *all* revisions of a schematic *on* the schematic. >I.e., lots of little "windows" showing portions of the schematic >as they existed previously. I think this is a poor man's way of >*not* using "proper" document retrieval systems (i.e., if I >need Rev C of a design, then I should fetch the Rev C documents!) Disagree, sorta. We put the revisions on the first page of the schematic and keep two or three (whatever fits). It's there as a reminder only and certainly doesn't supercede the ECO system. We also add notes to the schematic (in red) to incorporate if we ever hit the board again. Again, those are reminders only and don't supercede the problem reports and such. >I suspect there are many more that I just take for granted and >have failed to mention, here. :< *Somewhere* I have a document >formalizing all of these things. Though I suspect it is in >a format particular to a DTP program that I no longer have >on-line! :-/ Here's one. ;-) We have schematics that are essentially twelve itsy pages of schematics crammed onto one C-sized page. *Very* bad, though when I gagged during the interview it made big points with the engineering manager. ;-)
From: Tim Williams on 18 Jan 2010 20:21 "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message news:u0v9l5lk6k4tqlfrpef1b85msqju2trcd0(a)4ax.com... > PNP emitters up, NPN emitters down! Ah, but Tek doesn't do that -- IIRC (and maybe I don't), they often drew balanced circuits symmetrically, like so; http://webpages.charter.net/dawill/Images/Deflection%20Amp.gif The side-by-side approach is more common outside of oscilloscopes, but does lead to messier drawings because you're showing everything twice: http://webpages.charter.net/dawill/Images/Tube%20Oscilloscope%20Vertical.gif That, and the sheer number of passives indicated, is why this simple balanced amplifier is 1133 pixels wide. Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms
From: Tim Williams on 18 Jan 2010 20:24 I have one of those, actually. http://webpages.charter.net/dawill/tmoranwms/Elec_Circuit_Rules.html A bit dryer than conversation here, but gets the jist across. Motivation being I wrote my own cheapass's component library, so I might as well add something about its use. Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms "D Yuniskis" <not.going.to.be(a)seen.com> wrote in message news:hj2g7e$dcc$1(a)speranza.aioe.org... > I suspect there are many more that I just take for granted and > have failed to mention, here. :< *Somewhere* I have a document > formalizing all of these things. Though I suspect it is in > a format particular to a DTP program that I no longer have > on-line! :-/
From: krw on 18 Jan 2010 20:34 On Mon, 18 Jan 2010 16:26:51 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Mon, 18 Jan 2010 16:05:19 -0800, Jon Kirwan ><jonk(a)infinitefactors.org> wrote: > >>On Mon, 18 Jan 2010 13:37:16 -0700, D Yuniskis >><not.going.to.be(a)seen.com> wrote: >> >>>Of course, this is *highly* subjective -- but, I'd enjoy hearing >>>folks' "conventions" used when preparing schematics (that *others* >>>will consume -- how you scribble for your own purposes isn't >>>important as it depends a lot on what *you* want out of the >>>drawing). >>><snip> >> >>I was trained at Tektronix for drafting electronics, so my >>preferences come from there. >> >>>Aside from "general power", all signals that span pages *must* >>>come to the edge of the page. I don't like hunting for signals >>>in the middle of a page even if there is a grid reference to help >>>me locate it. It's just easier to conceptualize: "OK, this is >>>used elsewhere" or "This comes from someplace else" so I >>>know when something I am interested in involves other sheets. >>><snip> >> >>Let me state the following rules used at Tek: >> >>(1) Unless clearly justifiable for other reasons, electron >>flow from bottom of page upwards to the top. All parts >>oriented so that this is obvious. (No BJT spun around to >>make electron flow go otherwise, unless I can _justify_ >>clearly why it reads better.) > >PNP emitters up, NPN emitters down! That comes from +V on top, -V on the bottom. Op-amp: (-) on top of (+). D-FF: 'D' above 'Ck' (preset above D, Clear below Ck). Q above /Q
From: krw on 18 Jan 2010 20:37
On Mon, 18 Jan 2010 19:10:51 -0600, John Fields <jfields(a)austininstruments.com> wrote: >On Mon, 18 Jan 2010 16:13:23 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > > >>We use big (75 mils in PADS) dots. There's nothing wrong with a 4-way >>connection if the dots are obvious. > >--- >If one knows what's happening at that junction, that's fine, but it's >happened more than once that a drafting droid saw two lines crossing and >figured they should be connected. When was the last time you saw a drafting droid? ;-) >Resolving that ambiguity by breaking that "intersection" into two tees >disappears the problem. It takes valuable "routing" space. Signals should have as few bends as possible across the page. This gets important if all sheet inputs are on the left and outputs on the right. |