Schematic preferences
in [Design]
|
Prev: Oil sources Was: Re: Would magn. pole reversal actually mess up electronic equipment?
Next: Oil sources Was: Re: Would magn. pole reversal actually messup electronic equipment?
From: Robert Baer on 19 Jan 2010 19:47 krw wrote: > On Tue, 19 Jan 2010 01:17:19 -0700, D Yuniskis > <not.going.to.be(a)seen.com> wrote: > >> Hi John, >> >> John Fields wrote: >>> On Mon, 18 Jan 2010 16:13:23 -0800, John Larkin >>> >>>> We use big (75 mils in PADS) dots. There's nothing wrong with a 4-way >>>> connection if the dots are obvious. >>> If one knows what's happening at that junction, that's fine, but it's >>> happened more than once that a drafting droid saw two lines crossing and >>> figured they should be connected. >>> >>> Resolving that ambiguity by breaking that "intersection" into two tees >>> disappears the problem. >> That's how I used to draw things. But, I found it often resulted >> in clumsy signal routing -- just to avoid a 4WS. > > I'm with you. For hand' drawn schematics maybe 4WS avoidance is a > good thing. CAD does a much better job making things clearer. > >> I don't worry about people adding dots to *my* drawings. :> >> The bigger worry I have is when schematics are reproduced >> and it becomes difficult to determine if there is or isn't >> a dot on the junction. > > That's why OrCrap makes 'em red. ;-) A possible solution to avoid confusion and blotch botches: All 3 or 4 wire connections shown with de dots, if a wire must cross another but NOT connect, then use a half-circle to graphically show one "goes around" the other. Consistent use of this scheme gives: 1) If a blotch or mistraken dot is seen at a half-circle, then the obvious interpretation is correct and the blotch can be safely removed. 2) If 2 wires cross and there is nodot, then the obvious interpretation is correct and adot can be safely added. Ain't dot nice?
From: krw on 19 Jan 2010 19:50 On Tue, 19 Jan 2010 06:39:51 -0800 (PST), MooseFET <kensmith(a)rahul.net> wrote: >On Jan 18, 8:16�pm, krw <k...(a)att.bizzzzzzzzzzz> wrote: >> On Mon, 18 Jan 2010 18:39:06 -0800 (PST), MooseFET >> >> <kensm...(a)rahul.net> wrote: >> >> <snip> >> >> >All parts have the power pins shown. �The + is usually on the >> >top. �The exception is references and regulators where it is >> >on the left. >> >> What about gates? �All subcircuits get power pins? �What about dual >> op-amps? > >One of the parts of the op-amp show the power pins as does one logic >gate. I'd prefer the power be on a separate heterogeneous device, but this is second best. Many of our schematics have it on all op-amps (though gates get one power/ground per package). I'd prefer to have the power on a separate heterogeneous symbol so all of the gates can be interchangeable. >> <snip> >> >> >I never crossed lines as a connection point. �If two lines connect >> >to another line, they are offset. >> >> Again, that uses a additional "wiring channel" on the sheet. �Dots >> work fine. > >Dots have lead to errors. If the reproduction of the schematic is >less than perfect a mere fly spec can send the technician down a >blind alley. I think that's more of an issue with hand-drawn schematics. I haven't seen any problems (other than the damned software gets carried away with dots) with CAD packages. >[... ground symbols ...] > >What do you use for chassis ground? Pitchfork in the ground. >> is a digital grounds. �I know, they analog and digital grounds >> _should_ be the same. �They will be soon. �;-) > >You mean you don't flaot all your logic on the +5V plane? No, it hangs from it. ;-) > ------ > -----! 7805 !--------+--------- Logic Vcc > ------ > ! > +----------------------- Logic grounds > ! > /---/ 5.1V > ! > +----------------------- HC4051 Vee connections > GND > >I really did do this and the technicians didn't even kill me >for it. I avoided adding a switching device to make a minus >supply for the Vee and the minus swings. > >> >Mounting holes are shown if they have electrical meaning. >> >> Shields? > >Shields are soldered to "mounting holes" and schematically show >as a dashed line running through the hole and around the area. Our shields mount on solder balls. The balls are shown in the corner with a billion ground connections. I don't believe the components under the shield are shown (I agree, they should be).
From: krw on 19 Jan 2010 19:51 On Tue, 19 Jan 2010 05:26:50 -0800 (PST), mpm <mpmillard(a)aol.com> wrote: >On Jan 18, 3:37�pm, D Yuniskis <not.going.to...(a)seen.com> wrote: >> Hi, >> >> Of course, this is *highly* subjective -- but, I'd enjoy hearing >> folks' "conventions" used when preparing schematics (that *others* >> will consume -- how you scribble for your own purposes isn't >> important as it depends a lot on what *you* want out of the >> drawing). > > >My main rule (a preference actually) is that the same name be used in >the callouts when a circuit involves several schematic sheets! That's often difficult to do. It assumes single instances and no re-use. >I once worked for a video company that had a PLL circuit that >traversed 6 or 7 different circuit boards. >I guess each engineer / designer was responsible for his own board, >because none of the names matched up. >This made final device test & calibration very difficult. > >This device comprised roughly 75 "D-size" sheets of schematics. >I can still smell the ammonia from the Diazit copier..
From: krw on 19 Jan 2010 19:58 On Tue, 19 Jan 2010 10:22:40 -0800, "Joel Koltner" <zapwireDASHgroups(a)yahoo.com> wrote: >"mpm" <mpmillard(a)aol.com> wrote in message >news:3845b39c-4e2e-4e73-86b3-a5e9a27719a1(a)p8g2000yqb.googlegroups.com... >"I once worked for a video company that had a PLL circuit that >traversed 6 or 7 different circuit boards." > >That sounds familiar. We'll often have, e.g., an RF board, a digital board, a >display board, a power supply board -- or some assortment thereof -- and >different engineers working on each one. Out of necessity (chicken and the >egg problem) initially sometimes not all the net names for connectors going >between these boards match up, but by the time you're going to fab real >production boards they should. Getting everyone to agree on the names sooner >rather than later is better, though, as if 3 months have gone by people will >have sometimes become rather attached to *their* net name, used it in their >C/assembly/VHDL/Verilog/etc., and be more reluctant to change it to what "the >other guy" used. There should be a lead designer responsible for all of the interfaces to the component parts. In large projects we had someone assigned to "naming conventions", as well. He wrote the naming rules and assigned global signal names. >The main exception to that idea is when you have, e.g., serial transmit and >receive lines -- you don't want to just use "Tx" and "Rx" since one board's Tx >is the other's Rx. The best resolution there that I'm aware of is to label >one connector's nets, e.g., "uC_Tx" and "uC_Rx" on, say, the board with a >microcontroller on it, and then "DSP_Rx" and "DSP_Tx" on the board with the >DSP on it. (One could go for, e.g., uC_2_DSP_Tx everywhere, although that can >get overly wordy fast, and it still looks a little odd on the DSP board.) Yes, I generally name things by the "owner" of the interface, usually the processor. "DSP_Tx" and "DSP_Rx" would show up on the peripheral component's Rx and Tx lines, respectively. If they were different devices, then Tx and Rx would swap in the middle of a cable somewhere. >When labeling pins on "user definable" parts like FPGAs and microcontrollers, >I always have signal names be *with respect to that same part*. E.g., Tx, Rx, >Ready, Ack, Request, etc. -- that sort of thing. I name them WRT the "owner" of the bus. If the DSP controls the interface, the FPGA signals get the DSP's signal names.
From: Joel Koltner on 19 Jan 2010 19:59
"Robert Baer" <robertbaer(a)localnet.com> wrote in message news:puOdnTDeTaWpz8vWnZ2dnUVZ_jednZ2d(a)posted.localnet... > All 3 or 4 wire connections shown with de dots, if a wire must cross > another but NOT connect, then use a half-circle to graphically show one > "goes around" the other. Visio does this, but I've never met an actual schematic capture program that does. I'm not sure I'd want to use such a feature personally, but it would be a nice option, certainly. |